split register class handling from explicit physreg handling.
llvm-svn: 26308
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 243c51d..003d16c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -999,8 +999,8 @@
std::vector<unsigned> PPCTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) { // GCC RS6000 Constraint Letters
default: break; // Unknown constriant letter
@@ -1051,8 +1051,7 @@
}
}
- // Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+ return std::vector<unsigned>();
}
// isOperandValidForConstraint
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index a1ce554..86264ae 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -99,8 +99,8 @@
ConstraintType getConstraintType(char ConstraintLetter) const;
std::vector<unsigned>
- getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
};
}
diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp
index 79211de..e82e7f7 100644
--- a/llvm/lib/Target/TargetLowering.cpp
+++ b/llvm/lib/Target/TargetLowering.cpp
@@ -745,24 +745,34 @@
std::vector<unsigned> TargetLowering::
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
+ return std::vector<unsigned>();
+}
+
+
+std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
- // Not a physreg, must not be a register reference or something.
- if (Constraint[0] != '{') return std::vector<unsigned>();
+ if (Constraint[0] != '{')
+ return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
// Remove the braces from around the name.
std::string RegName(Constraint.begin()+1, Constraint.end()-1);
-
- // Scan to see if this constraint is a register name.
+
+ // Figure out which register class contains this reg.
const MRegisterInfo *RI = TM.getRegisterInfo();
- for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
- if (const char *Name = RI->get(i).Name)
- if (StringsEqualNoCase(RegName, Name))
- return std::vector<unsigned>(1, i);
+ for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
+ E = RI->regclass_end(); RCI != E; ++RCI) {
+ const TargetRegisterClass *RC = *RCI;
+ for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
+ I != E; ++I) {
+ if (StringsEqualNoCase(RegName, RI->get(*I).Name)) {
+ return std::make_pair(*I, RC);
+ }
+ }
}
- // Unknown physreg.
- return std::vector<unsigned>();
+ return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
}
-
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bbf590b..e32cc0f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1961,8 +1961,8 @@
}
std::vector<unsigned> X86TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
// FIXME: not handling MMX registers yet ('y' constraint).
@@ -1993,6 +1993,5 @@
}
}
- // Handle explicit register names.
- return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+ return std::vector<unsigned>();
}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 375320c..d45afa4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -224,8 +224,8 @@
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
std::vector<unsigned>
- getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ getRegClassForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
private:
// C Calling Convention implementation.
std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);