commit 7b3d162fba795b6db258ab835b43953e59629478
author Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Tue Mar 20 12:58:34 2018 +0000
committer Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> Tue Mar 20 12:58:34 2018 +0000
tree b2406eca8bd57b7b43f43000748ecd677a36f3b5
parent e92ecd3196db3612a3ee06b2d195adff26fa2019

[llvm-mca] Use llvm::make_unique in a few places. NFC

Also, clang-format a couple of DEBUG functions.

llvm-svn: 327978

llvm/tools/llvm-mca/Backend.cpp

diff --git a/llvm/tools/llvm-mca/Backend.cpp b/llvm/tools/llvm-mca/Backend.cpp
index 8d34175..cad7db3 100644
--- a/llvm/tools/llvm-mca/Backend.cpp
+++ b/llvm/tools/llvm-mca/Backend.cpp
@@ -33,8 +33,8 @@
 
   while (SM.hasNext()) {
     InstRef IR = SM.peekNext();
-    std::unique_ptr<Instruction> NewIS(
-        IB->createInstruction(IR.first, *IR.second));
+    std::unique_ptr<Instruction> NewIS =
+        IB->createInstruction(IR.first, *IR.second);
     const InstrDesc &Desc = NewIS->getDesc();
     if (!DU->isAvailable(Desc.NumMicroOps) ||
         !DU->canDispatch(IR.first, *NewIS))
@@ -80,5 +80,4 @@
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleEnd(Cycle);
 }
-
 } // namespace mca.

llvm/tools/llvm-mca/InstrBuilder.cpp

diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index 1bf2b36..82b5f16 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -112,12 +112,12 @@
     }
   }
 
-  DEBUG(
+  DEBUG({
     for (const std::pair<uint64_t, ResourceUsage> &R : ID.Resources)
       dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n';
     for (const uint64_t R : ID.Buffers)
       dbgs() << "\t\tBuffer Mask=" << R << '\n';
-  );
+  });
 }
 
 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc,
@@ -260,11 +260,10 @@
     }
     Write.FullyUpdatesSuperRegs = FullyUpdatesSuperRegisters;
     Write.IsOptionalDef = false;
-    DEBUG(
-      dbgs() << "\t\tOpIdx=" << Write.OpIndex
-             << ", Latency=" << Write.Latency << ", WriteResourceID="
-             << Write.SClassOrWriteResourceID << '\n';
-    );
+    DEBUG({
+      dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
+             << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
+    });
     CurrentDef++;
   }
 
@@ -371,7 +370,7 @@
       *SM.getSchedClassDesc(MCDesc.getSchedClass());
 
   // Create a new empty descriptor.
-  InstrDesc *ID = new InstrDesc();
+  std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
 
   if (SCDesc.isVariant()) {
     errs() << "warning: don't know how to model variant opcodes.\n"
@@ -406,7 +405,7 @@
   DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
 
   // Now add the new descriptor.
-  Descriptors[Opcode] = std::unique_ptr<const InstrDesc>(ID);
+  Descriptors[Opcode] = std::move(ID);
 }
 
 const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
@@ -416,9 +415,10 @@
   return *Descriptors[MCI.getOpcode()].get();
 }
 
-Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
+std::unique_ptr<Instruction>
+InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
   const InstrDesc &D = getOrCreateInstrDesc(MCI);
-  Instruction *NewIS = new Instruction(D);
+  std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
 
   // Populate Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
@@ -441,8 +441,7 @@
 
     // Okay, this is a register operand. Create a ReadState for it.
     assert(RegID > 0 && "Invalid register ID found!");
-    ReadState *NewRDS = new ReadState(RD, RegID);
-    NewIS->getUses().emplace_back(std::unique_ptr<ReadState>(NewRDS));
+    NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID));
   }
 
   // Now populate writes.
@@ -455,12 +454,9 @@
     if (WD.IsOptionalDef && !RegID)
       continue;
 
-    WriteState *NewWS = new WriteState(WD);
-    NewIS->getDefs().emplace_back(std::unique_ptr<WriteState>(NewWS));
-    NewWS->setRegisterID(RegID);
+    NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(WD, RegID));
   }
 
   return NewIS;
 }
-
 } // namespace mca

llvm/tools/llvm-mca/InstrBuilder.h

diff --git a/llvm/tools/llvm-mca/InstrBuilder.h b/llvm/tools/llvm-mca/InstrBuilder.h
index a26b846..d31ccef 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.h
+++ b/llvm/tools/llvm-mca/InstrBuilder.h
@@ -53,7 +53,8 @@
 
   const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI);
 
-  Instruction *createInstruction(unsigned Idx, const llvm::MCInst &MCI);
+  std::unique_ptr<Instruction> createInstruction(unsigned Idx,
+                                                 const llvm::MCInst &MCI);
 };
 } // namespace mca
 

llvm/tools/llvm-mca/Instruction.h

diff --git a/llvm/tools/llvm-mca/Instruction.h b/llvm/tools/llvm-mca/Instruction.h
index a760193..a87420d 100644
--- a/llvm/tools/llvm-mca/Instruction.h
+++ b/llvm/tools/llvm-mca/Instruction.h
@@ -102,8 +102,8 @@
   std::set<std::pair<ReadState *, int>> Users;
 
 public:
-  WriteState(const WriteDescriptor &Desc)
-      : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(Desc.RegisterID) {}
+  WriteState(const WriteDescriptor &Desc, unsigned RegID)
+      : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID) {}
   WriteState(const WriteState &Other) = delete;
   WriteState &operator=(const WriteState &Other) = delete;