commit 7bff8f1d7adfaa5d6de77100445eab0d3676de27
author Reed Kotler <rkotler@mips.com> Thu Dec 20 06:06:35 2012 +0000
committer Reed Kotler <rkotler@mips.com> Thu Dec 20 06:06:35 2012 +0000
tree 1c464e075b7cf62c4fd99cefbb77ca9b412b81f5
parent fb8ac2df0914cb3f37fdc8bab43de24213beadd6

set register class properly for mips16 here

llvm-svn: 170669

llvm/lib/Target/Mips/MipsISelLowering.cpp

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index e3abd3e..dd44adb 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3099,7 +3099,8 @@
       const TargetRegisterClass *RC;
 
       if (RegVT == MVT::i32)
-        RC = &Mips::CPURegsRegClass;
+        RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
+                                        &Mips::CPURegsRegClass;
       else if (RegVT == MVT::i64)
         RC = &Mips::CPU64RegsRegClass;
       else if (RegVT == MVT::f32)