commit 7c20aab621c25c209472e906816f48b7c9945321
author Bill Wendling <isanbard@gmail.com> Thu Aug 22 20:46:05 2013 +0000
committer Bill Wendling <isanbard@gmail.com> Thu Aug 22 20:46:05 2013 +0000
tree 18ce807d84369293d8b120c69b754b1d9174f94d
parent c2ecf0d815450b8a4c8ff3f9f78ecd9bd29b57ab

FileCheckize some tests.

llvm-svn: 189060

llvm/test/TableGen/LetInsideMultiClasses.td

diff --git a/llvm/test/TableGen/LetInsideMultiClasses.td b/llvm/test/TableGen/LetInsideMultiClasses.td
index 72f48b6..cfa756d 100644
--- a/llvm/test/TableGen/LetInsideMultiClasses.td
+++ b/llvm/test/TableGen/LetInsideMultiClasses.td
@@ -1,4 +1,9 @@
-// RUN: llvm-tblgen %s | grep "bit IsDouble = 1;" | count 3
+// RUN: llvm-tblgen %s | FileCheck %s
+
+// CHECK: bit IsDouble = 1;
+// CHECK: bit IsDouble = 1;
+// CHECK: bit IsDouble = 1;
+// CHECK-NOT: bit IsDouble = 1;
 
 class Instruction<bits<4> opc, string Name> {
   bits<4> opcode = opc;