commit 7c2bf62b1403f55a894a6d776f5236c11311673d
author Dan Gohman <gohman@apple.com> Thu Aug 14 22:53:18 2008 +0000
committer Dan Gohman <gohman@apple.com> Thu Aug 14 22:53:18 2008 +0000
tree 5d6b9ece6294c7739aa4816d857f0953345c6857
parent 4f6bf04616b01fef8740ff68427a8ae0c570b923

Also avoid pinsrw and pinsrb with a variable insertelement index.

llvm-svn: 54803

llvm/lib/Target/X86/X86ISelLowering.cpp

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6b95034..6488a1a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4143,7 +4143,8 @@
   SDValue N1 = Op.getOperand(1);
   SDValue N2 = Op.getOperand(2);
 
-  if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) {
+  if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
+      isa<ConstantSDNode>(N2)) {
     unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
                                                   : X86ISD::PINSRW;
     // Transform it so it match pinsr{b,w} which expects a GR32 as its second