commit 7d522b6eee0cac4427ee36f770284ec23ed690b5
author Craig Topper <craig.topper@intel.com> Tue Apr 03 06:37:01 2018 +0000
committer Craig Topper <craig.topper@intel.com> Tue Apr 03 06:37:01 2018 +0000
tree d5fdb3c7ba3f8d272d1b81b7c98d025a019a3663
parent c01e47b43f46a1fe2ad95245fad71b21341abe64

[X86][TableGen] Add a missing error check to make sure EVEX instructions use one PS/PD/XS/XD prefixes.

llvm-svn: 329048

llvm/utils/TableGen/X86RecognizableInstr.cpp

diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index a387efb..5811528 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -243,8 +243,12 @@
       insnContext = EVEX_KB(IC_EVEX_XD);
     else if (OpPrefix == X86Local::XS)
       insnContext = EVEX_KB(IC_EVEX_XS);
-    else
+    else if (OpPrefix == X86Local::PS)
       insnContext = EVEX_KB(IC_EVEX);
+    else {
+      errs() << "Instruction does not use a prefix: " << Name << "\n";
+      llvm_unreachable("Invalid prefix");
+    }
     /// eof EVEX
   } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
     if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) {