Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
llvm-svn: 47532
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.h b/llvm/lib/Target/CellSPU/SPUISelLowering.h
index 847c668..a6147bf 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.h
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.h
@@ -50,12 +50,15 @@
MPYU, ///< Multiply Unsigned
MPYH, ///< Multiply High
MPYHH, ///< Multiply High-High
+ SHLQUAD_L_BITS, ///< Rotate quad left, by bits
+ SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
VEC_SHL, ///< Vector shift left
VEC_SRL, ///< Vector shift right (logical)
VEC_SRA, ///< Vector shift right (arithmetic)
VEC_ROTL, ///< Vector rotate left
VEC_ROTR, ///< Vector rotate right
- ROTBYTES_RIGHT_Z, ///< Vector rotate right, by bytes, zero fill
+ ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill
+ ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill
ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill
ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain