| commit | 7d7adf4f2e4e50f738a5f692e6f011dcfca6b070 | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Thu Dec 14 22:34:10 2017 +0000 |
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Thu Dec 14 22:34:10 2017 +0000 |
| tree | df846d9653c67e5bcd684da57d8dc97665c057b3 | |
| parent | c7bc461298d540cefec9ffe370f68dfbca367e8b [diff] [blame] |
TLI: Allow using PSV for intrinsic mem operands llvm-svn: 320756
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index dd5e964..d3e2e11 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -558,6 +558,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &CI, + MachineFunction &MF, unsigned IntrID) const { switch (IntrID) { case Intrinsic::amdgcn_atomic_inc: