commit 7d7adf4f2e4e50f738a5f692e6f011dcfca6b070
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Dec 14 22:34:10 2017 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Dec 14 22:34:10 2017 +0000
tree df846d9653c67e5bcd684da57d8dc97665c057b3
parent c7bc461298d540cefec9ffe370f68dfbca367e8b

TLI: Allow using PSV for intrinsic mem operands

llvm-svn: 320756

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b3db306..718e09a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2261,6 +2261,7 @@
 /// passed to the function.
 bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                                const CallInst &I,
+                                               MachineFunction &MF,
                                                unsigned Intrinsic) const {
   switch (Intrinsic) {
   case Intrinsic::hexagon_V6_vgathermw: