Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
sequence of a pair of i32->i64 extensions followed by a "bitwise or"
into COMBINE_rr.
* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
* test/CodeGen/Hexagon/union-1.ll: New test.
* test/CodeGen/Hexagon/combine_ir.ll: Fix test.
llvm-svn: 180946
diff --git a/llvm/test/CodeGen/Hexagon/combine_ir.ll b/llvm/test/CodeGen/Hexagon/combine_ir.ll
index 921ce99..8b99ef7 100644
--- a/llvm/test/CodeGen/Hexagon/combine_ir.ll
+++ b/llvm/test/CodeGen/Hexagon/combine_ir.ll
@@ -6,12 +6,7 @@
entry:
%0 = load i32* %a, align 4, !tbaa !0
%1 = zext i32 %0 to i64
- %add.ptr = getelementptr inbounds i32* %a, i32 1
- %2 = load i32* %add.ptr, align 4, !tbaa !0
- %3 = zext i32 %2 to i64
- %4 = shl nuw i64 %3, 32
- %ins = or i64 %4, %1
- tail call void @bar(i64 %ins) nounwind
+ tail call void @bar(i64 %1) nounwind
ret void
}
diff --git a/llvm/test/CodeGen/Hexagon/union-1.ll b/llvm/test/CodeGen/Hexagon/union-1.ll
new file mode 100644
index 0000000..7c6da74
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/union-1.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; CHECK: word
+; CHECK-NOT: combine(#0
+; CHECK: jump bar
+
+define void @word(i32* nocapture %a) nounwind {
+entry:
+ %0 = load i32* %a, align 4, !tbaa !0
+ %1 = zext i32 %0 to i64
+ %add.ptr = getelementptr inbounds i32* %a, i32 1
+ %2 = load i32* %add.ptr, align 4, !tbaa !0
+ %3 = zext i32 %2 to i64
+ %4 = shl nuw i64 %3, 32
+ %ins = or i64 %4, %1
+ tail call void @bar(i64 %ins) nounwind
+ ret void
+}
+
+declare void @bar(i64)
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}