For PR950:
Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.
llvm-svn: 31195
diff --git a/llvm/lib/VMCore/Instruction.cpp b/llvm/lib/VMCore/Instruction.cpp
index b295146..c5e8e30 100644
--- a/llvm/lib/VMCore/Instruction.cpp
+++ b/llvm/lib/VMCore/Instruction.cpp
@@ -94,7 +94,9 @@
case Add: return "add";
case Sub: return "sub";
case Mul: return "mul";
- case Div: return "div";
+ case UDiv: return "udiv";
+ case SDiv: return "sdiv";
+ case FDiv: return "fdiv";
case Rem: return "rem";
// Logical operators...
@@ -221,7 +223,9 @@
///
bool Instruction::isTrapping(unsigned op) {
switch(op) {
- case Div:
+ case UDiv:
+ case SDiv:
+ case FDiv:
case Rem:
case Load:
case Store: