commit 7eb55b395fdbbdbd113aabb6cad51cc98b379af0
author Reid Spencer <rspencer@reidspencer.com> Thu Nov 02 01:53:59 2006 +0000
committer Reid Spencer <rspencer@reidspencer.com> Thu Nov 02 01:53:59 2006 +0000
tree 2666f67e03e73fc890b7277073186b32ead86d50
parent 57382066e875c05e58f35db5976a22ed5dcdebf8

For PR950:
Replace the REM instruction with UREM, SREM and FREM.

llvm-svn: 31369

llvm/lib/VMCore/Instructions.cpp

diff --git a/llvm/lib/VMCore/Instructions.cpp b/llvm/lib/VMCore/Instructions.cpp
index 790f6ac..3825d85 100644
--- a/llvm/lib/VMCore/Instructions.cpp
+++ b/llvm/lib/VMCore/Instructions.cpp
@@ -1023,7 +1023,6 @@
   switch (iType) {
   case Add: case Sub:
   case Mul: 
-  case Rem:
     assert(getType() == LHS->getType() &&
            "Arithmetic operation should return same type as operands!");
     assert((getType()->isInteger() || getType()->isFloatingPoint() ||
@@ -1045,7 +1044,21 @@
             cast<PackedType>(getType())->getElementType()->isFloatingPoint())) 
             && "Incorrect operand type (not floating point) for FDIV");
     break;
-
+  case URem: 
+  case SRem: 
+    assert(getType() == LHS->getType() &&
+           "Arithmetic operation should return same type as operands!");
+    assert((getType()->isInteger() || (isa<PackedType>(getType()) && 
+            cast<PackedType>(getType())->getElementType()->isInteger())) &&
+           "Incorrect operand type (not integer) for S/UREM");
+    break;
+  case FRem:
+    assert(getType() == LHS->getType() &&
+           "Arithmetic operation should return same type as operands!");
+    assert((getType()->isFloatingPoint() || (isa<PackedType>(getType()) &&
+            cast<PackedType>(getType())->getElementType()->isFloatingPoint())) 
+            && "Incorrect operand type (not floating point) for FREM");
+    break;
   case And: case Or:
   case Xor:
     assert(getType() == LHS->getType() &&