commit 7efc04cb40a602f0d51c12d2ab55b30882d6cb5f
author Nadav Rotem <nrotem@apple.com> Wed Aug 21 05:03:10 2013 +0000
committer Nadav Rotem <nrotem@apple.com> Wed Aug 21 05:03:10 2013 +0000
tree e59c64651231e0ec35be02ead1896a4327add7bb
parent 092559e6f07316d7607e77769ae34a70cabbd687

In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.

Patch by Chris Bieneman.

llvm-svn: 188866

llvm/lib/Target/X86/X86CodeEmitter.cpp

diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index 5d72b44..0f9c562 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -985,8 +985,14 @@
       if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
         VEX_R = 0x0;
 
-      if (HasVEX_4V)
-        VEX_4V = getVEXRegisterEncoding(MI, 1);
+      if (HasVEX_4V) {
+        if (HasMemOp4)
+          VEX_4V = getVEXRegisterEncoding(MI, 1);
+        else
+          // FMA3 instructions operands are dst, src1, src2, src3
+          // dst and src1 are the same and not encoded separately
+          VEX_4V = getVEXRegisterEncoding(MI, 2);
+      }
 
       if (X86II::isX86_64ExtendedReg(
                           MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))