More swift calling convention tests
llvm-svn: 285417
diff --git a/llvm/test/CodeGen/ARM/swift-return.ll b/llvm/test/CodeGen/ARM/swift-return.ll
index 4a5ef5e..f8cc7fc 100644
--- a/llvm/test/CodeGen/ARM/swift-return.ll
+++ b/llvm/test/CodeGen/ARM/swift-return.ll
@@ -131,3 +131,184 @@
}
declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
+
+; The return value {float, float, float, float} will be returned via registers
+; s0-s3.
+; CHECK-LABEL: test4:
+; CHECK: bl _gen4
+; CHECK: vadd.f32 s0, s0, s1
+; CHECK: vadd.f32 s0, s0, s2
+; CHECK: vadd.f32 s0, s0, s3
+; CHECK-O0-LABEL: test4:
+; CHECK-O0: bl _gen4
+; CHECK-O0: vadd.f32 s0, s0, s1
+; CHECK-O0: vadd.f32 s0, s0, s2
+; CHECK-O0: vadd.f32 s0, s0, s3
+define float @test4(float %key) #0 {
+entry:
+ %key.addr = alloca float, align 4
+ store float %key, float* %key.addr, align 4
+ %0 = load float, float* %key.addr, align 4
+ %call = call swiftcc { float, float, float, float } @gen4(float %0)
+
+ %v3 = extractvalue { float, float, float, float } %call, 0
+ %v5 = extractvalue { float, float, float, float } %call, 1
+ %v6 = extractvalue { float, float, float, float } %call, 2
+ %v7 = extractvalue { float, float, float, float } %call, 3
+
+ %add = fadd float %v3, %v5
+ %add1 = fadd float %add, %v6
+ %add2 = fadd float %add1, %v7
+ ret float %add2
+}
+
+declare swiftcc { float, float, float, float } @gen4(float %key)
+
+; CHECK-LABEL: test5
+; CHECK: bl _gen5
+; CHECK: vadd.f64 [[TMP:d.*]], d0, d1
+; CHECK: vadd.f64 [[TMP]], [[TMP]], d2
+; CHECK: vadd.f64 d0, [[TMP]], d3
+define swiftcc double @test5() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double } @gen5()
+
+ %v3 = extractvalue { double, double, double, double } %call, 0
+ %v5 = extractvalue { double, double, double, double } %call, 1
+ %v6 = extractvalue { double, double, double, double } %call, 2
+ %v7 = extractvalue { double, double, double, double } %call, 3
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+ ret double %add2
+}
+
+declare swiftcc { double, double, double, double } @gen5()
+
+
+; CHECK-LABEL: test6
+; CHECK: bl _gen6
+; CHECK-DAG: vadd.f64 [[TMP:d.*]], d0, d1
+; CHECK-DAG: add r0, r0, r1
+; CHECK-DAG: add r0, r0, r2
+; CHECK-DAG: add r0, r0, r3
+; CHECK-DAG: vadd.f64 [[TMP]], [[TMP]], d2
+; CHECK-DAG: vadd.f64 d0, [[TMP]], d3
+define swiftcc { double, i32 } @test6() #0 {
+entry:
+ %call = call swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+ %v3 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 0
+ %v5 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 1
+ %v6 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 2
+ %v7 = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 3
+ %v3.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 4
+ %v5.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 5
+ %v6.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 6
+ %v7.i = extractvalue { double, double, double, double, i32, i32, i32, i32 } %call, 7
+
+ %add = fadd double %v3, %v5
+ %add1 = fadd double %add, %v6
+ %add2 = fadd double %add1, %v7
+
+ %add.i = add nsw i32 %v3.i, %v5.i
+ %add1.i = add nsw i32 %add.i, %v6.i
+ %add2.i = add nsw i32 %add1.i, %v7.i
+
+ %Y = insertvalue { double, i32 } undef, double %add2, 0
+ %Z = insertvalue { double, i32 } %Y, i32 %add2.i, 1
+ ret { double, i32} %Z
+}
+
+declare swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
+
+; CHECK-LABEL: gen7
+; CHECK: mov r1, r0
+; CHECK: mov r2, r0
+; CHECK: mov r3, r0
+; CHECK: bx lr
+define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
+ %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0
+ %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1
+ %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2
+ %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3
+ ret { i32, i32, i32, i32 } %v3
+}
+
+; CHECK-LABEL: gen9
+; CHECK: mov r1, r0
+; CHECK: mov r2, r0
+; CHECK: mov r3, r0
+; CHECK: bx lr
+define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
+ %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
+ %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1
+ %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2
+ %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3
+ ret { i8, i8, i8, i8 } %v3
+}
+; CHECK-LABEL: gen10
+; CHECK-DAG: vmov.f64 d1, d0
+; CHECK-DAG: mov r1, r0
+; CHECK-DAG: mov r2, r0
+; CHECK-DAG: mov r3, r0
+; CHECK-DAG: vmov.f64 d2, d0
+; CHECK-DAG: vmov.f64 d3, d0
+; CHECK-DAG: bx lr
+define swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen10(double %keyd, i32 %keyi) {
+ %v0 = insertvalue { double, double, double, double, i32, i32, i32, i32 } undef, double %keyd, 0
+ %v1 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v0, double %keyd, 1
+ %v2 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v1, double %keyd, 2
+ %v3 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v2, double %keyd, 3
+ %v4 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v3, i32 %keyi, 4
+ %v5 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v4, i32 %keyi, 5
+ %v6 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v5, i32 %keyi, 6
+ %v7 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v6, i32 %keyi, 7
+ ret { double, double, double, double, i32, i32, i32, i32 } %v7
+}
+
+
+; CHECK-LABEL: test11
+; CHECK: bl _gen11
+; CHECK: vadd.f32 [[TMP:q.*]], q0, q1
+; CHECK: vadd.f32 [[TMP]], [[TMP]], q2
+; CHECK: vadd.f32 q0, [[TMP]], q3
+define swiftcc <4 x float> @test11() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2
+ %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %add2 = fadd <4 x float> %add1, %v7
+ ret <4 x float> %add2
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
+
+; CHECK-LABEL: test12
+; CHECK-DAG: vadd.f32 [[TMP:q.*]], q0, q1
+; CHECK-DAG: vmov.f32 s4, s12
+; CHECK-DAG: vadd.f32 q0, [[TMP]], q2
+define swiftcc { <4 x float>, float } @test12() #0 {
+entry:
+ %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
+
+ %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0
+ %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1
+ %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2
+ %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3
+
+ %add = fadd <4 x float> %v3, %v5
+ %add1 = fadd <4 x float> %add, %v6
+ %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0
+ %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1
+ ret { <4 x float>, float } %res
+}
+
+declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll
index 2559560..3540283 100644
--- a/llvm/test/CodeGen/ARM/swifterror.ll
+++ b/llvm/test/CodeGen/ARM/swifterror.ll
@@ -394,3 +394,124 @@
%0 = tail call swiftcc float @tailcallswifterror_swiftcc(%swift_error** swifterror %error_ptr_ref)
ret float %0
}
+
+; CHECK-APPLE-LABEL: swifterror_clobber
+; CHECK-APPLE: mov [[REG:r[0-9]+]], r6
+; CHECK-APPLE: nop
+; CHECK-APPLE: mov r6, [[REG]]
+define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
+ call void asm sideeffect "nop", "~{r6}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: swifterror_reg_clobber
+; CHECK-APPLE: push {{.*}}r6
+; CHECK-APPLE: nop
+; CHECK-APPLE: pop {{.*}}r6
+define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
+ call void asm sideeffect "nop", "~{r6}"()
+ ret void
+}
+
+; CHECK-APPLE-LABEL: _params_in_reg
+; Store callee saved registers excluding swifterror.
+; CHECK-APPLE: push {r8, r10, r11, r4, r5, r7, lr}
+; Store swiftself (r10) and swifterror (r6).
+; CHECK-APPLE: str r6, [sp, #4]
+; CHECK-APPLE: str r10, [sp]
+; Store arguments.
+; CHECK-APPLE: mov r4, r3
+; CHECK-APPLE: mov r5, r2
+; CHECK-APPLE: mov r8, r1
+; CHECK-APPLE: mov r11, r0
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: mov r6, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Restore original arguments.
+; CHECK-APPLE: ldr r10, [sp]
+; CHECK-APPLE: ldr r6, [sp, #4]
+; CHECK-APPLE: mov r0, r11
+; CHECK-APPLE: mov r1, r8
+; CHECK-APPLE: mov r2, r5
+; CHECK-APPLE: mov r3, r4
+; CHECK-APPLE: bl _params_in_reg2
+; CHECK-APPLE: sub sp, r7, #20
+; CHECK-APPLE: pop {r8, r10, r11, r4, r5, r7, pc}
+define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ call swiftcc void @params_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
+ ret void
+}
+declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
+
+; CHECK-LABEL: params_and_return_in_reg
+; CHECK-APPLE: push {r8, r10, r11, r4, r5, r7, lr}
+; Store swifterror and swiftself
+; CHECK-APPLE: mov r4, r6
+; CHECK-APPLE: str r10, [sp, #12]
+; Store arguments.
+; CHECK-APPLE: str r3, [sp, #8]
+; CHECK-APPLE: mov r5, r2
+; CHECK-APPLE: mov r8, r1
+; CHECK-APPLE: mov r11, r0
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: mov r6, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Restore original arguments.
+; CHECK-APPLE: ldr r3, [sp, #8]
+; CHECK-APPLE: ldr r10, [sp, #12]
+; Store %error_ptr_ref;
+; CHECK-APPLE: str r6, [sp, #4]
+; Restore original arguments.
+; CHECK-APPLE: mov r0, r11
+; CHECK-APPLE: mov r1, r8
+; CHECK-APPLE: mov r2, r5
+; CHECK-APPLE: mov r6, r4
+; CHECK-APPLE: bl _params_and_return_in_reg2
+; Store swifterror return %err;
+; CHECK-APPLE: str r6, [sp, #12]
+; Load swifterror value %error_ptr_ref.
+; CHECK-APPLE: ldr r6, [sp, #4]
+; Save return values.
+; CHECK-APPLE: mov r5, r0
+; CHECK-APPLE: mov r4, r1
+; CHECK-APPLE: mov r8, r2
+; CHECK-APPLE: mov r11, r3
+; Setup call.
+; CHECK-APPLE: mov r0, #1
+; CHECK-APPLE: mov r1, #2
+; CHECK-APPLE: mov r2, #3
+; CHECK-APPLE: mov r3, #4
+; CHECK-APPLE: mov r10, #0
+; CHECK-APPLE: bl _params_in_reg2
+; Load swifterror %err;
+; CHECK-APPLE: ldr r6, [sp, #12]
+; Restore return values for returning.
+; CHECK-APPLE: mov r0, r5
+; CHECK-APPLE: mov r1, r4
+; CHECK-APPLE: mov r2, r8
+; CHECK-APPLE: mov r3, r11
+; CHECK-APPLE: sub sp, r7, #20
+; CHECK-APPLE: pop {r8, r10, r11, r4, r5, r7, pc}
+define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
+ %error_ptr_ref = alloca swifterror %swift_error*, align 8
+ store %swift_error* null, %swift_error** %error_ptr_ref
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ %val = call swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32 %0, i32 %1, i32 %2, i32 %3, i8* swiftself %4, %swift_error** nocapture swifterror %err)
+ call swiftcc void @params_in_reg2(i32 1, i32 2, i32 3, i32 4, i8* swiftself null, %swift_error** nocapture swifterror %error_ptr_ref)
+ ret { i32, i32, i32, i32 }%val
+}
+
+declare swiftcc { i32, i32, i32, i32 } @params_and_return_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)