Changes to build successfully with GCC 3.02
llvm-svn: 1503
diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp
index fb2888b..098da90 100644
--- a/llvm/lib/Target/Sparc/EmitAssembly.cpp
+++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp
@@ -22,16 +22,17 @@
#include "Support/StringExtras.h"
#include "Support/HashExtras.h"
#include <locale.h>
+using std::string;
namespace {
class SparcAsmPrinter {
- typedef hash_map<const Value*, int> ValIdMap;
+ typedef std::hash_map<const Value*, int> ValIdMap;
typedef ValIdMap:: iterator ValIdMapIterator;
typedef ValIdMap::const_iterator ValIdMapConstIterator;
- ostream &toAsm;
+ std::ostream &toAsm;
SlotCalculator Table; // map anonymous values to unique integer IDs
ValIdMap valToIdMap; // used for values not handled by SlotCalculator
const UltraSparc &Target;
@@ -45,7 +46,7 @@
} CurSection;
public:
- inline SparcAsmPrinter(ostream &o, const Module *M, const UltraSparc &t)
+ inline SparcAsmPrinter(std::ostream &o, const Module *M, const UltraSparc &t)
: toAsm(o), Table(SlotCalculator(M, true)), Target(t), CurSection(Unknown) {
emitModule(M);
}
@@ -61,7 +62,7 @@
void printGlobalVariable( const GlobalVariable* GV);
void printSingleConstant( const Constant* CV);
void printConstantValueOnly(const Constant* CV);
- void printConstant( const Constant* CV, string valID=string(""));
+ void printConstant( const Constant* CV, std::string valID = "");
unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
void printOneOperand(const MachineOperand &Op);
@@ -88,7 +89,7 @@
toAsm << "\n";
}
- string getValidSymbolName(const string &S) {
+ std::string getValidSymbolName(const string &S) {
string Result;
// Symbol names in Sparc assembly language have these rules:
@@ -318,7 +319,7 @@
case MachineOperand::MO_SignExtendedImmed:
case MachineOperand::MO_UnextendedImmed:
- toAsm << op.getImmedValue();
+ toAsm << (long)op.getImmedValue();
break;
default:
@@ -351,7 +352,7 @@
else
N = 1;
- toAsm << endl;
+ toAsm << "\n";
}
void
@@ -393,7 +394,7 @@
// Output a .size directive so the debugger knows the extents of the function
toAsm << ".EndOf_" << methName << ":\n\t.size "
<< methName << ", .EndOf_"
- << methName << "-" << methName << endl;
+ << methName << "-" << methName << "\n";
// Put some spaces between the methods
toAsm << "\n\n";
@@ -487,7 +488,6 @@
inline unsigned int
ConstantToAlignment(const Constant* CV, const TargetMachine& target)
{
- unsigned int constantSize;
if (ConstantArray* CPA = dyn_cast<ConstantArray>(CV))
if (ArrayTypeIsString(cast<ArrayType>(CPA->getType())))
return SizeToAlignment(1 + CPA->getNumOperands(), target);
@@ -515,16 +515,15 @@
{
if (CV->getType() == Type::FloatTy || CV->getType() == Type::DoubleTy)
toAsm << "0r"; // FP constants must have this prefix
- toAsm << CV->getStrValue() << endl;
+ toAsm << CV->getStrValue() << "\n";
}
else if (ConstantPointer* CPP = dyn_cast<ConstantPointer>(CV))
{
- if (! CPP->isNullValue())
- assert(0 && "Cannot yet print non-null pointer constants to assembly");
- else
- toAsm << (void*) NULL << endl;
+ assert(CPP->isNullValue() &&
+ "Cannot yet print non-null pointer constants to assembly");
+ toAsm << "0\n";
}
- else if (ConstantPointerRef* CPRef = dyn_cast<ConstantPointerRef>(CV))
+ else if (isa<ConstantPointerRef>(CV))
{
assert(0 && "Cannot yet initialize pointer refs in assembly");
}
@@ -543,17 +542,17 @@
if (CPA && isStringCompatible(CPA))
{ // print the string alone and return
- toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << endl;
+ toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << "\n";
}
else if (CPA)
{ // Not a string. Print the values in successive locations
- const vector<Use>& constValues = CPA->getValues();
+ const std::vector<Use> &constValues = CPA->getValues();
for (unsigned i=1; i < constValues.size(); i++)
this->printConstantValueOnly(cast<Constant>(constValues[i].get()));
}
else if (ConstantStruct *CPS = dyn_cast<ConstantStruct>(CV))
{ // Print the fields in successive locations
- const vector<Use>& constValues = CPS->getValues();
+ const std::vector<Use>& constValues = CPS->getValues();
for (unsigned i=1; i < constValues.size(); i++)
this->printConstantValueOnly(cast<Constant>(constValues[i].get()));
}
@@ -571,25 +570,25 @@
valID = getID(CV);
toAsm << "\t.align\t" << ConstantToAlignment(CV, Target)
- << endl;
+ << "\n";
// Print .size and .type only if it is not a string.
ConstantArray *CPA = dyn_cast<ConstantArray>(CV);
if (CPA && isStringCompatible(CPA))
{ // print it as a string and return
- toAsm << valID << ":" << endl;
- toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << endl;
+ toAsm << valID << ":\n";
+ toAsm << "\t" << ".ascii" << "\t" << getAsCString(CPA) << "\n";
return;
}
- toAsm << "\t.type" << "\t" << valID << ",#object" << endl;
+ toAsm << "\t.type" << "\t" << valID << ",#object\n";
unsigned int constSize = ConstantToSize(CV, Target);
if (constSize)
toAsm << "\t.size" << "\t" << valID << ","
- << constSize << endl;
+ << constSize << "\n";
- toAsm << valID << ":" << endl;
+ toAsm << valID << ":\n";
this->printConstantValueOnly(CV);
}
@@ -598,29 +597,29 @@
void
SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV)
{
- toAsm << "\t.global\t" << getID(GV) << endl;
+ toAsm << "\t.global\t" << getID(GV) << "\n";
if (GV->hasInitializer())
printConstant(GV->getInitializer(), getID(GV));
else {
toAsm << "\t.align\t"
- << TypeToAlignment(GV->getType()->getElementType(), Target) << endl;
- toAsm << "\t.type\t" << getID(GV) << ",#object" << endl;
+ << TypeToAlignment(GV->getType()->getElementType(), Target) << "\n";
+ toAsm << "\t.type\t" << getID(GV) << ",#object\n";
toAsm << "\t.reserve\t" << getID(GV) << ","
<< TypeToSize(GV->getType()->getElementType(), Target)
- << endl;
+ << "\n";
}
}
static void
FoldConstants(const Module *M,
- hash_set<const Constant*>& moduleConstants)
+ std::hash_set<const Constant*>& moduleConstants)
{
for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I)
if (! (*I)->isExternal())
{
- const hash_set<const Constant*>& pool =
+ const std::hash_set<const Constant*>& pool =
MachineCodeForMethod::get(*I).getConstantPoolValues();
moduleConstants.insert(pool.begin(), pool.end());
}
@@ -636,7 +635,7 @@
// lets force these constants into the slot table so that we can get
// unique names for unnamed constants also.
//
- hash_set<const Constant*> moduleConstants;
+ std::hash_set<const Constant*> moduleConstants;
FoldConstants(M, moduleConstants);
// Now, emit the three data sections separately; the cost of I/O should
@@ -654,7 +653,8 @@
}
}
- for (hash_set<const Constant*>::const_iterator I = moduleConstants.begin(),
+ for (std::hash_set<const Constant*>::const_iterator
+ I = moduleConstants.begin(),
E = moduleConstants.end(); I != E; ++I)
printConstant(*I);
@@ -682,7 +682,7 @@
}
}
- toAsm << endl;
+ toAsm << "\n";
}
@@ -705,7 +705,7 @@
// used.
//
void
-UltraSparc::emitAssembly(const Module *M, ostream &toAsm) const
+UltraSparc::emitAssembly(const Module *M, std::ostream &toAsm) const
{
SparcAsmPrinter Print(toAsm, M, *this);
}
diff --git a/llvm/lib/Target/Sparc/Sparc.cpp b/llvm/lib/Target/Sparc/Sparc.cpp
index 9524e80..dd9e330 100644
--- a/llvm/lib/Target/Sparc/Sparc.cpp
+++ b/llvm/lib/Target/Sparc/Sparc.cpp
@@ -17,7 +17,8 @@
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
#include "llvm/Method.h"
-
+#include <iostream>
+using std::cerr;
// Build the MachineInstruction Description Array...
const MachineInstrDescriptor SparcMachineInstrDesc[] = {
@@ -47,10 +48,9 @@
if ( (M)->isExternal() ) // don't process prototypes
return;
- if( DEBUG_RA ) {
- cerr << endl << "******************** Method "<< (M)->getName();
- cerr << " ********************" <<endl;
- }
+ if( DEBUG_RA )
+ cerr << "\n******************** Method "<< M->getName()
+ << " ********************\n";
MethodLiveVarInfo LVI(M ); // Analyze live varaibles
LVI.analyze();
@@ -60,7 +60,7 @@
PRA.allocateRegisters();
- if( DEBUG_RA ) cerr << endl << "Register allocation complete!" << endl;
+ if( DEBUG_RA ) cerr << "\nRegister allocation complete!\n";
}
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 99bb14d..e00c871 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -27,7 +27,7 @@
static inline MachineInstr*
CreateIntSetInstruction(int64_t C, Value* dest,
- vector<TmpInstruction*>& tempVec)
+ std::vector<TmpInstruction*>& tempVec)
{
MachineInstr* minstr;
uint64_t absC = (C >= 0)? C : -C;
@@ -55,7 +55,7 @@
static inline MachineInstr*
CreateUIntSetInstruction(uint64_t C, Value* dest,
- vector<TmpInstruction*>& tempVec)
+ std::vector<TmpInstruction*>& tempVec)
{
MachineInstr* minstr;
if (C > (unsigned int) ~0)
@@ -109,9 +109,9 @@
//
void
UltraSparcInstrInfo::CreateCodeToLoadConst(Value* val,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec) const
+ Instruction* dest,
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*>& tempVec) const
{
MachineInstr* minstr;
@@ -200,19 +200,17 @@
//
void
UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Method* method,
- Value* val,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
- TargetMachine& target) const
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const
{
assert((val->getType()->isIntegral() || val->getType()->isPointerType())
&& "Source type must be integral");
assert((dest->getType() ==Type::FloatTy || dest->getType() ==Type::DoubleTy)
&& "Dest type must be float/double");
- const MachineFrameInfo& frameInfo = ((UltraSparc&) target).getFrameInfo();
-
MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(method);
int offset = mcinfo.allocateLocalVar(target, val);
@@ -246,19 +244,17 @@
//
void
UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(Method* method,
- Value* val,
- Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
- TargetMachine& target) const
+ Value* val,
+ Instruction* dest,
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const
{
assert((val->getType() ==Type::FloatTy || val->getType() ==Type::DoubleTy)
&& "Source type must be float/double");
assert((dest->getType()->isIntegral() || dest->getType()->isPointerType())
&& "Dest type must be integral");
- const MachineFrameInfo& frameInfo = ((UltraSparc&) target).getFrameInfo();
-
MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(method);
int offset = mcinfo.allocateLocalVar(target, val);
diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
index c4fe735..c20c65a 100644
--- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
@@ -25,7 +25,7 @@
#include "llvm/ConstantVals.h"
#include "Support/MathExtras.h"
#include <math.h>
-
+using std::vector;
//************************* Forward Declarations ***************************/
@@ -34,7 +34,7 @@
const InstructionNode* vmInstrNode,
Value* ptrVal,
Value* arrayOffsetVal,
- const vector<Value*>& idxVec,
+ const std::vector<Value*>& idxVec,
const TargetMachine& target);
@@ -143,7 +143,7 @@
static TmpInstruction*
GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
{
- typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
+ typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache;
static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
static const Method* lastMethod = NULL; // Use to flush cache between methods
@@ -519,7 +519,6 @@
{
MachineInstr* minstr = NULL; // return NULL if we cannot exploit constant
getMinstr2 = NULL; // to create a cheaper instruction
- bool needNeg = false;
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
assert(isa<Constant>(constOp));
@@ -1011,8 +1010,6 @@
TargetMachine &target,
MachineInstr** mvec)
{
- int64_t s0=0; // used to avoid overloading ambiguity below
-
const MachineFrameInfo& frameInfo = target.getFrameInfo();
// The second operand is the stack size. If it does not fit in the
@@ -1048,11 +1045,10 @@
TargetMachine &target,
MachineInstr** mvec)
{
- int64_t s0=0; // used to avoid overloading ambiguity below
-
mvec[0] = new MachineInstr(RESTORE);
mvec[0]->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
+ mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
+ (int64_t)0);
mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
return 1;
@@ -1118,8 +1114,6 @@
bool checkCast = false; // initialize here to use fall-through
int nextRule;
int forwardOperandNum = -1;
- int64_t s0=0, s8=8; // variables holding constants to avoid
- uint64_t u0=0; // overloading ambiguities below
for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++)
mvec[i] = NULL;
@@ -1162,7 +1156,8 @@
mvec[0] = new MachineInstr(JMPLRET);
mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
returnReg);
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s8);
+ mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
+ (int64_t)8);
mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
if (returnInstr->getReturnValue() != NULL)
@@ -1775,7 +1770,7 @@
int n = numInstr++;
mvec[n] = new MachineInstr(SETHI);
mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,
- s0);
+ (int64_t)0);
mvec[n]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
setCCInstr);
}
@@ -2021,7 +2016,7 @@
phi->getOperand(i));
break;
}
-#endif NEED_PHI_MACHINE_INSTRS
+#endif // NEED_PHI_MACHINE_INSTRS
case 71: // reg: VReg
case 72: // reg: Constant
diff --git a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
index f62457c..848dddd 100644
--- a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
+++ b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
@@ -58,4 +58,4 @@
return 0;
}
-#endif SPARC_INSTR_SELECTION_SUPPORT_h
+#endif
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index 51609f6..a82d122 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -128,8 +128,8 @@
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec) const;
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*>& tmp) const;
// Create an instruction sequence to copy an integer value `val'
@@ -141,8 +141,8 @@
virtual void CreateCodeToCopyIntToFloat(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstr,
+ std::vector<TmpInstruction*>& temp,
TargetMachine& target) const;
// Similarly, create an instruction sequence to copy an FP value
@@ -152,8 +152,8 @@
virtual void CreateCodeToCopyFloatToInt(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstr,
+ std::vector<TmpInstruction*>& temp,
TargetMachine& target) const;
// create copy instruction(s)
@@ -161,7 +161,7 @@
CreateCopyInstructionsByType(const TargetMachine& target,
Value* src,
Instruction* dest,
- vector<MachineInstr*>& minstrVec) const;
+ std::vector<MachineInstr*>& minstr) const;
};
@@ -245,7 +245,7 @@
LiveRangeInfo& LRI) const;
void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
- vector<RegClass *> RCList) const;
+ std::vector<RegClass *> RCList) const;
@@ -348,12 +348,13 @@
// the register allocator in association with method calling. See
// SparcRegInfo.cpp for more details
//
- void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
- PhyRegAlloc &PRA ) const;
+ void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
+ MachineInstr *UnordInst,
+ PhyRegAlloc &PRA) const;
- void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
- vector<MachineInstr *> &OrdVec,
- PhyRegAlloc &PRA) const;
+ void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
+ std::vector<MachineInstr *> &OrdVec,
+ PhyRegAlloc &PRA) const;
// To find whether a particular call is to a var arg method
@@ -410,7 +411,7 @@
else if( ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
else {
- cerr << "TypeID: " << ty << endl;
+ std::cerr << "TypeID: " << ty << "\n";
assert(0 && "Cannot resolve register class for type");
return 0;
}
@@ -449,10 +450,11 @@
LiveRangeInfo& LRI) const;
void suggestRegs4CallArgs(const MachineInstr *const CallMI,
- LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
+ LiveRangeInfo& LRI,
+ std::vector<RegClass *> RCL) const;
void suggestReg4RetValue(const MachineInstr *const RetMI,
- LiveRangeInfo& LRI ) const;
+ LiveRangeInfo& LRI) const;
void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
@@ -493,7 +495,7 @@
// given the unified register number, this gives the name
// for generating assembly code or debugging.
//
- inline const string getUnifiedRegName(int reg) const {
+ inline const std::string getUnifiedRegName(int reg) const {
if( reg < 32 )
return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) )
@@ -513,7 +515,7 @@
// The fllowing methods are used by instruction selection
//
- inline unsigned int getRegNumInCallersWindow(int reg) {
+ inline unsigned getRegNumInCallersWindow(int reg) {
if (reg == InvalidRegNum || reg >= 32)
return reg;
return SparcIntRegOrder::getRegNumInCallersWindow(reg);
@@ -1433,7 +1435,7 @@
// module. The specified module must have been compiled before this may be
// used.
//
- virtual void emitAssembly(const Module *M, ostream &OutStr) const;
+ virtual void emitAssembly(const Module *M, std::ostream &OutStr) const;
};
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
index 6b39d61..709a8f4 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
@@ -1,7 +1,8 @@
-#include "llvm/CodeGen/IGNode.h"
#include "SparcInternals.h"
-
+#include "llvm/CodeGen/IGNode.h"
#include "llvm/Target/Sparc.h"
+#include <iostream>
+using std::cerr;
//-----------------------------------------------------------------------------
// Int Register Class - method for coloring a node in the interference graph.
@@ -37,7 +38,7 @@
}
if( DEBUG_RA ) {
- cout << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
+ cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
LR->printSet();
}
@@ -53,18 +54,18 @@
// there are no call interferences. Otherwise, it will get spilled.
if (DEBUG_RA)
- cout << "\n -Coloring with sug color: " << SugCol;
+ cerr << "\n -Coloring with sug color: " << SugCol;
LR->setColor( LR->getSuggestedColor() );
return;
}
else if(DEBUG_RA)
- cout << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
+ cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
}
else if ( DEBUG_RA ) { // can't allocate the suggested col
cerr << " \n Could NOT allocate the suggested color (already used) ";
- LR->printSet(); cerr << endl;
+ LR->printSet(); cerr << "\n";
}
}
@@ -91,7 +92,7 @@
if( ColorFound) {
LR->setColor(c); // first color found in preffered order
- if (DEBUG_RA) cout << "\n Colored after first search with col " << c ;
+ if (DEBUG_RA) cerr << "\n Colored after first search with col " << c ;
}
// if color is not found because of call interference
@@ -113,7 +114,7 @@
// since LR span across calls, must save across calls
//
LR->markForSaveAcrossCalls();
- if(DEBUG_RA) cout << "\n Colored after SECOND search with col " << c ;
+ if(DEBUG_RA) cerr << "\n Colored after SECOND search with col " << c ;
}
}
@@ -193,7 +194,7 @@
}
else if (DEBUG_RA) { // can't allocate the suggested col
cerr << " Could NOT allocate the suggested color for LR ";
- LR->printSet(); cerr << endl;
+ LR->printSet(); cerr << "\n";
}
}
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
index 0a5f516..9127ffd 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
@@ -17,7 +17,7 @@
// Int register names in same order as enum in class SparcIntRegOrder
-static string const IntRegNames[] =
+static const std::string IntRegNames[] =
{
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
@@ -75,7 +75,7 @@
static unsigned int const NumOfAllRegs = o6 + 1;
- static const string getRegName(const unsigned reg) {
+ static const std::string getRegName(const unsigned reg) {
assert( reg < NumOfAllRegs );
return IntRegNames[reg];
}
@@ -119,7 +119,7 @@
// Float Register Class
//-----------------------------------------------------------------------------
-static string const FloatRegNames[] =
+static const std::string FloatRegNames[] =
{
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
@@ -157,7 +157,7 @@
static unsigned int const StartOfAllRegs = f0;
- static const string getRegName(const unsigned reg) {
+ static const std::string getRegName(const unsigned reg) {
assert( reg < NumOfAllRegs );
return FloatRegNames[reg];
}
@@ -203,7 +203,7 @@
//-----------------------------------------------------------------------------
-static string const IntCCRegNames[] =
+static const std::string IntCCRegNames[] =
{
"xcc", "ccr"
};
@@ -218,7 +218,7 @@
xcc, ccr // only one is available - see the note above
};
- static const string getRegName(const unsigned reg) {
+ static const std::string getRegName(const unsigned reg) {
assert( reg < 2 );
return IntCCRegNames[reg];
}
@@ -253,7 +253,7 @@
//-----------------------------------------------------------------------------
-static string const FloatCCRegNames[] =
+static const std::string FloatCCRegNames[] =
{
"fcc0", "fcc1", "fcc2", "fcc3"
};
@@ -268,7 +268,7 @@
fcc0, fcc1, fcc2, fcc3
};
- static const string getRegName(const unsigned reg) {
+ static const std::string getRegName(const unsigned reg) {
assert( reg < 4 );
return FloatCCRegNames[reg];
}
diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 6543397..dcfc5fa 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -8,6 +8,8 @@
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/DerivedTypes.h"
+#include <iostream>
+using std::cerr;
//---------------------------------------------------------------------------
// Purpose:
@@ -21,11 +23,10 @@
//---------------------------------------------------------------------------
const Value *
UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
-
unsigned OpCode = CallMI->getOpCode();
- unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
+ unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
- if( OpCode == CALL ) {
+ if (OpCode == CALL) {
// The one before the last implicit operand is the return value of
// a CALL instr
@@ -34,14 +35,13 @@
if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
return CallMI->getImplicitRef(NumOfImpRefs-2);
- }
- else if( OpCode == JMPLCALL) {
+ } else if (OpCode == JMPLCALL) {
// The last implicit operand is the return value of a JMPL
//
- if( NumOfImpRefs > 0 )
- if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
- return CallMI->getImplicitRef(NumOfImpRefs-1);
+ if(NumOfImpRefs > 0)
+ if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
+ return CallMI->getImplicitRef(NumOfImpRefs-1);
}
else
assert(0 && "OpCode must be CALL/JMPL for a call instr");
@@ -189,7 +189,7 @@
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
LiveRangeInfo& LRI,
- vector<RegClass *> RCList) const {
+ std::vector<RegClass *> RCList) const {
const Value *RetAddrVal = getCallInstRetAddr( CallMI );
@@ -361,10 +361,8 @@
// that on to the stack pos of LR
if( isArgInReg ) {
-
- MachineInstr *AdIBef =
- cpReg2MemMI(UniArgReg, getFramePointer(),
- LR->getSpillOffFromFP(), RegType );
+ cpReg2MemMI(UniArgReg, getFramePointer(),
+ LR->getSpillOffFromFP(), RegType );
FirstAI->InstrnsBefore.push_back( AdMI );
}
@@ -404,7 +402,7 @@
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
LiveRangeInfo& LRI,
- vector<RegClass *> RCList) const {
+ std::vector<RegClass *> RCList) const {
assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
@@ -469,7 +467,7 @@
if( !LR ) {
if( DEBUG_RA) {
cerr << " ERROR: In call instr, no LR for arg: " ;
- printValue(CallArg); cerr << endl;
+ printValue(CallArg); cerr << "\n";
}
assert(0 && "NO LR for call arg");
// continue;
@@ -485,7 +483,7 @@
else if (DEBUG_RA)
// Do NOTHING as this will be colored as a normal value.
- cerr << " Regr not suggested for int call arg" << endl;
+ cerr << " Regr not suggested for int call arg\n";
}
else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
@@ -535,7 +533,7 @@
if( !RetValLR ) {
cerr << "\nNo LR for:";
printValue( RetVal );
- cerr << endl;
+ cerr << "\n";
assert( RetValLR && "ERR:No LR for non-void return value");
//return;
}
@@ -601,7 +599,7 @@
// Now color all args of the call instruction
//-------------------------------------------
- vector <MachineInstr *> AddedInstrnsBefore;
+ std::vector<MachineInstr *> AddedInstrnsBefore;
unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
@@ -662,7 +660,7 @@
if( !LR ) {
if( DEBUG_RA) {
cerr << " ERROR: In call instr, no LR for arg: " ;
- printValue(CallArg); cerr << endl;
+ printValue(CallArg); cerr << "\n";
}
assert(0 && "NO LR for call arg");
// continue;
@@ -812,7 +810,7 @@
cerr << *(AddedInstrnsBefore[i]);
}
- vector <MachineInstr *> TmpVec;
+ std::vector<MachineInstr *> TmpVec;
OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
if( DEBUG_RA ) {
@@ -855,13 +853,12 @@
// The first implicit operand is the return value of a return instr
const Value *RetVal = RetMI->getImplicitRef(0);
- MachineInstr *AdMI;
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
if( !LR ) {
cerr << "\nNo LR for:";
printValue( RetVal );
- cerr << endl;
+ cerr << "\n";
assert( LR && "No LR for return value of non-void method");
//return;
}
@@ -898,13 +895,12 @@
// The first implicit operand is the return value of a return instr
const Value *RetVal = RetMI->getImplicitRef(0);
- MachineInstr *AdMI;
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
if( ! LR ) {
cerr << "\nNo LR for:";
printValue( RetVal );
- cerr << endl;
+ cerr << "\n";
// assert( LR && "No LR for return value of non-void method");
return;
}
@@ -941,16 +937,14 @@
// the LR received UniLRReg but must be colored with UniRetReg
// to pass as the return value
-
- AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType);
- RetAI->InstrnsBefore.push_back( AdMI );
+ RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType));
}
else { // if the LR is spilled
-
- AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
- UniRetReg, RegType);
- RetAI->InstrnsBefore.push_back( AdMI );
- cout << "\nCopied the return value from stack";
+ MachineInstr *AdMI = cpMem2RegMI(getFramePointer(),
+ LR->getSpillOffFromFP(),
+ UniRetReg, RegType);
+ RetAI->InstrnsBefore.push_back(AdMI);
+ cerr << "\nCopied the return value from stack\n";
}
} // if there is a return value
@@ -1179,9 +1173,7 @@
// has set to record which registers were saved/restored
//
- hash_set<unsigned> PushedRegSet;
-
-
+ std::hash_set<unsigned> PushedRegSet;
// Now find the LR of the return value of the call
// The last *implicit operand* is the return value of a call
@@ -1394,7 +1386,7 @@
cerr << " *Node " << (LR->getUserIGNode())->getIndex();
if( ! LR->hasColor() ) {
- cerr << " - could not find a color" << endl;
+ cerr << " - could not find a color\n";
return;
}
@@ -1403,15 +1395,13 @@
cerr << " colored with color "<< LR->getColor();
if( RegClassID == IntRegClassID ) {
+ cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
- cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
- cerr << "]" << endl;
- }
- else if ( RegClassID == FloatRegClassID) {
+ } else if ( RegClassID == FloatRegClassID) {
cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
if( LR->getTypeID() == Type::DoubleTyID )
cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
- cerr << "]" << endl;
+ cerr << "]\n";
}
}
@@ -1436,9 +1426,9 @@
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
- vector<MachineInstr *> &OrdVec,
- PhyRegAlloc &PRA) const{
+void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
+ std::vector<MachineInstr *> &OrdVec,
+ PhyRegAlloc &PRA) const{
/*
Problem: We can have instructions inserted by RegAlloc like
@@ -1476,7 +1466,7 @@
CouldMoveAll = true;
- vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
+ std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
for( ; DefIt != UnordVec.end(); ++DefIt ) {
@@ -1498,7 +1488,7 @@
bool DefEqUse = false;
- vector<MachineInstr *>::iterator UseIt = DefIt;
+ std::vector<MachineInstr *>::iterator UseIt = DefIt;
UseIt++;
for( ; UseIt != UnordVec.end(); ++UseIt ) {
@@ -1572,7 +1562,7 @@
-void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec,
+void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
MachineInstr *UnordInst,
PhyRegAlloc &PRA ) const {
@@ -1585,7 +1575,7 @@
// before in the OrdVec
bool DefEqUse = false;
- vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
+ std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {