[DebugInfo] Examine all uses of isDebugValue() for debug instructions.
Because we create a new kind of debug instruction, DBG_LABEL, we need to
check all passes which use isDebugValue() to check MachineInstr is debug
instruction or not. When expelling debug instructions, we should expel
both DBG_VALUE and DBG_LABEL. So, I create a new function,
isDebugInstr(), in MachineInstr to check whether the MachineInstr is
debug instruction or not.
This patch has no new test case. I have run regression test and there is
no difference in regression test.
Differential Revision: https://reviews.llvm.org/D45342
Patch by Hsiangkai Wang.
llvm-svn: 331844
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
index b0bda7c..9ff2472 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
@@ -392,7 +392,7 @@
// Check all instructions, except the terminators. It is assumed that
// terminators never have side effects or define any used register values.
for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
- if (I.isDebugValue())
+ if (I.isDebugInstr())
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index d233827..2523cfd 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -162,7 +162,7 @@
// realistically that's not a big deal at this stage of the game.
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue() || MI.isPseudo() ||
+ if (MI.isDebugInstr() || MI.isPseudo() ||
MI.getOpcode() == AArch64::ADDXri ||
MI.getOpcode() == AArch64::ADDSXri)
continue;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 452bb13..879d91d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5044,7 +5044,7 @@
return MachineOutlinerInstrType::Illegal;
// Don't allow debug values to impact outlining type.
- if (MI.isDebugValue() || MI.isIndirectDebugValue())
+ if (MI.isDebugInstr() || MI.isIndirectDebugValue())
return MachineOutlinerInstrType::Invisible;
// At this point, KILL instructions don't really tell us much so we can go
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 9cb9045..2a05e3b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -511,7 +511,7 @@
// TODO: CodeSize should account for multiple functions.
// TODO: Should we count size of debug info?
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
CodeSize += TII->getInstSizeInBytes(MI);
@@ -652,7 +652,7 @@
continue;
case AMDGPU::NoRegister:
- assert(MI.isDebugValue());
+ assert(MI.isDebugInstr());
continue;
case AMDGPU::VCC:
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index dd515b0..20f1321 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -634,7 +634,7 @@
}
int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
return 0;
const SIRegisterInfo *TRI = ST.getRegisterInfo();
diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
index 9fecd85..bf84139 100644
--- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
@@ -69,14 +69,14 @@
auto I = Begin;
MaxInstNum = std::max(MaxInstNum, 1u);
for (; I != End && MaxInstNum; ++I, --MaxInstNum) {
- if (!I->isDebugValue() && LIS)
+ if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;
}
if (I != End) {
OS << "\t...\n";
I = std::prev(End);
- if (!I->isDebugValue() && LIS)
+ if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;
}
@@ -384,10 +384,10 @@
if (MI != &*Top) {
BB->remove(MI);
BB->insert(Top, MI);
- if (!MI->isDebugValue())
+ if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);
}
- if (!MI->isDebugValue()) {
+ if (!MI->isDebugInstr()) {
// Reset read - undef flags and update them later.
for (auto &Op : MI->operands())
if (Op.isReg() && Op.isDef())
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index a294ae0..4e569a2 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -301,7 +301,7 @@
LastTrackedMI = &MI;
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return;
auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index cd7ccb4..f92788e 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -388,13 +388,13 @@
DEBUG(dbgs() << "Attempting to revert scheduling.\n");
RegionEnd = RegionBegin;
for (MachineInstr *MI : Unsched) {
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
continue;
if (MI->getIterator() != RegionEnd) {
BB->remove(MI);
BB->insert(RegionEnd, MI);
- if (!MI->isDebugValue())
+ if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);
}
// Reset read-undef flags and update them later.
@@ -403,7 +403,7 @@
Op.setIsUndef(false);
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
- if (!MI->isDebugValue()) {
+ if (!MI->isDebugInstr()) {
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
diff --git a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp
index 69ec381..c8ae8f7 100644
--- a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp
+++ b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp
@@ -78,8 +78,8 @@
for (auto &MBB : MF) {
for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {
- // Skip DBG_VALUE instructions and instructions without location.
- if (MI->isDebugValue() || !MI->getDebugLoc())
+ // Skip debug instructions and instructions without location.
+ if (MI->isDebugInstr() || !MI->getDebugLoc())
continue;
// Insert nop instruction if line number does not have nop inserted.
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 7dc3b68..e6aaaf9 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -897,7 +897,7 @@
setForceEmitWaitcnt();
bool IsForceEmitWaitcnt = isForceEmitWaitcnt();
- if (MI.isDebugValue() &&
+ if (MI.isDebugInstr() &&
// TODO: any other opcode?
!NeedLineMapping) {
return;
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index 04536cd..0fd4c6b 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -1280,7 +1280,7 @@
nextIfDebug(MachineBasicBlock::iterator I,
MachineBasicBlock::const_iterator End) {
for (; I != End; ++I) {
- if (!I->isDebugValue())
+ if (!I->isDebugInstr())
break;
}
return I;
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index 51ac814..b7bb80a 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -134,7 +134,7 @@
}
while (I != E) {
- if (I->isDebugValue()) {
+ if (I->isDebugInstr()) {
I = std::next(I);
continue;
}
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 4a95fce..f8d14d2 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -173,7 +173,7 @@
bool CantAnalyze = false;
// Skip over DEBUG values and predicated nonterminators.
- while (I->isDebugValue() || !I->isTerminator()) {
+ while (I->isDebugInstr() || !I->isTerminator()) {
if (I == MBB.begin())
return false;
--I;
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 89e2236..efe96f8 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -331,7 +331,7 @@
bool CantAnalyze = false;
// Skip over DEBUG values and predicated nonterminators.
- while (I->isDebugValue() || !I->isTerminator()) {
+ while (I->isDebugInstr() || !I->isTerminator()) {
if (I == MBB.begin())
return false;
--I;
@@ -1815,7 +1815,7 @@
// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return false;
// Terminators and labels can't be scheduled around.
@@ -1829,8 +1829,8 @@
// to the t2IT instruction. The added compile time and complexity does not
// seem worth it.
MachineBasicBlock::const_iterator I = MI;
- // Make sure to skip any dbg_value instructions
- while (++I != MBB->end() && I->isDebugValue())
+ // Make sure to skip any debug instructions
+ while (++I != MBB->end() && I->isDebugInstr())
;
if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
return true;
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 7411caf..1e3655a 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -701,7 +701,7 @@
WaterList.push_back(&MBB);
for (MachineInstr &I : MBB) {
- if (I.isDebugValue())
+ if (I.isDebugInstr())
continue;
unsigned Opc = I.getOpcode();
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index f878bf9..d5dacbe 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -37,7 +37,7 @@
MachineInstr *MI = SU->getInstr();
- if (!MI->isDebugValue()) {
+ if (!MI->isDebugInstr()) {
// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
// a VMLA / VMLS will cause 4 cycle stall.
const MCInstrDesc &MCID = MI->getDesc();
@@ -81,7 +81,7 @@
void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
MachineInstr *MI = SU->getInstr();
- if (!MI->isDebugValue()) {
+ if (!MI->isDebugInstr()) {
LastMI = MI;
FpMLxStalls = 0;
}
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index bd47870..174ed3e 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1198,7 +1198,7 @@
// Skip debug values.
MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
- while (PrevMBBI->isDebugValue() && PrevMBBI != BeginMBBI)
+ while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
--PrevMBBI;
Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
@@ -1214,7 +1214,7 @@
MachineBasicBlock::iterator EndMBBI = MBB.end();
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
// Skip debug values.
- while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
+ while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
++NextMBBI;
if (NextMBBI == EndMBBI)
return EndMBBI;
@@ -1807,7 +1807,7 @@
MBBI = I;
--Position;
// Fallthrough to look into existing chain.
- } else if (MBBI->isDebugValue()) {
+ } else if (MBBI->isDebugInstr()) {
continue;
} else if (MBBI->getOpcode() == ARM::t2LDRDi8 ||
MBBI->getOpcode() == ARM::t2STRDi8) {
@@ -1891,8 +1891,8 @@
MBBI->getOpcode() == ARM::tBX_RET ||
MBBI->getOpcode() == ARM::MOVPCLR)) {
MachineBasicBlock::iterator PrevI = std::prev(MBBI);
- // Ignore any DBG_VALUE instructions.
- while (PrevI->isDebugValue() && PrevI != MBB.begin())
+ // Ignore any debug instructions.
+ while (PrevI->isDebugInstr() && PrevI != MBB.begin())
--PrevI;
MachineInstr &PrevMI = *PrevI;
unsigned Opcode = PrevMI.getOpcode();
@@ -2063,7 +2063,7 @@
// Are there stores / loads / calls between them?
SmallSet<unsigned, 4> AddedRegPressure;
while (++I != E) {
- if (I->isDebugValue() || MemOps.count(&*I))
+ if (I->isDebugInstr() || MemOps.count(&*I))
continue;
if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
return false;
@@ -2253,7 +2253,7 @@
// This is the new location for the loads / stores.
MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
while (InsertPos != MBB->end() &&
- (MemOps.count(&*InsertPos) || InsertPos->isDebugValue()))
+ (MemOps.count(&*InsertPos) || InsertPos->isDebugInstr()))
++InsertPos;
// If we are moving a pair of loads / stores, see if it makes sense
@@ -2355,7 +2355,7 @@
break;
}
- if (!MI.isDebugValue())
+ if (!MI.isDebugInstr())
MI2LocMap[&MI] = ++Loc;
if (!isMemoryOp(MI))
diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
index 04bdd91..e0a5f7f 100644
--- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -183,7 +183,7 @@
// If not, then there is nothing to be gained by moving the copy.
MachineBasicBlock::iterator I = MI; ++I;
MachineBasicBlock::iterator E = MI->getParent()->end();
- while (I != E && I->isDebugValue())
+ while (I != E && I->isDebugInstr())
++I;
if (I != E) {
unsigned NPredReg = 0;
@@ -237,7 +237,7 @@
// block so check the instruction we just put in the block.
for (; MBBI != E && Pos &&
(!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
- if (MBBI->isDebugValue())
+ if (MBBI->isDebugInstr())
continue;
MachineInstr *NMI = &*MBBI;
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 179f113..d5f0ba9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -82,7 +82,7 @@
MachineBasicBlock::iterator E = MBB->begin();
unsigned Count = 4; // At most 4 instructions in an IT block.
while (Count && MBBI != E) {
- if (MBBI->isDebugValue()) {
+ if (MBBI->isDebugInstr()) {
--MBBI;
continue;
}
@@ -109,7 +109,7 @@
bool
Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const {
- while (MBBI->isDebugValue()) {
+ while (MBBI->isDebugInstr()) {
++MBBI;
if (MBBI == MBB.end())
return false;
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index 5357e26..115ba65 100644
--- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -1033,7 +1033,7 @@
BundleMI = MI;
continue;
}
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
continue;
LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index 5e0818b..e4bdd40 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -475,7 +475,7 @@
// before that instead and adjust the UseMI.
bool done = false;
for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
- if (II->isDebugValue())
+ if (II->isDebugInstr())
continue;
// If this instruction affects R12, adjust our restore point.
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index 1a89a13..0c32334 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -273,7 +273,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue()) {
+ if (I->isDebugInstr()) {
continue;
}
@@ -444,7 +444,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue()) {
+ if (I->isDebugInstr()) {
continue;
}
//:TODO: add here the missing jmp instructions once they are implemented
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index ffb7acd..ab6d7c8 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -93,7 +93,7 @@
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator
@@ -168,7 +168,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (I->getOpcode() != BPF::JMP)
break;
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 378aafb..69529b0 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -843,7 +843,7 @@
void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace)
dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return;
assert(!MI.isBranch() && "Unexpected branch instruction");
diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 6b836e2..0ac83ea 100644
--- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -760,7 +760,7 @@
MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
- if (!MII->isDebugValue() && !MII->isImplicitDef())
+ if (!MII->isDebugInstr() && !MII->isImplicitDef())
HexagonLowerToMC(MCII, &*MII, MCB, *this);
} else {
HexagonLowerToMC(MCII, MI, MCB, *this);
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index 8153c49..2fb30df 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -160,7 +160,7 @@
IndexType Idx = IndexType::First;
First = Idx;
for (auto &In : B) {
- if (In.isDebugValue())
+ if (In.isDebugInstr())
continue;
assert(getIndex(&In) == IndexType::None && "Instruction already in map");
Map.insert(std::make_pair(Idx, &In));
@@ -314,7 +314,7 @@
RegisterSet Defs, Clobbers;
for (auto &In : B) {
- if (In.isDebugValue())
+ if (In.isDebugInstr())
continue;
IndexType Index = IndexMap.getIndex(&In);
// Process uses first.
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 62b2e89..730cfaf 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -799,7 +799,7 @@
SetVector<const MachineBasicBlock*> &Targets) {
MachineBasicBlock::const_iterator FirstBr = MB->end();
for (const MachineInstr &MI : *MB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
if (MI.isBranch()) {
FirstBr = MI.getIterator();
@@ -814,7 +814,7 @@
for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) {
const MachineInstr &MI = *I;
// Can there be debug instructions between branches?
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
if (!InstrExec.count(&MI))
continue;
@@ -896,7 +896,7 @@
// If the successor block just became executable, visit all instructions.
// To see if this is the first time we're visiting it, check the first
// non-debug instruction to see if it is executable.
- while (It != End && It->isDebugValue())
+ while (It != End && It->isDebugInstr())
++It;
assert(It == End || !It->isPHI());
// If this block has been visited, go on to the next one.
@@ -905,7 +905,7 @@
// For now, scan all non-branch instructions. Branches require different
// processing.
while (It != End && !It->isBranch()) {
- if (!It->isDebugValue()) {
+ if (!It->isDebugInstr()) {
InstrExec.insert(&*It);
visitNonBranch(*It);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 087a772..f3d2473 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -300,7 +300,7 @@
// * reads I2's def reg
// * or has unmodelled side effects
// we can't move I2 across it.
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
@@ -358,7 +358,7 @@
// to remove the implicit killed %d4 operand. For now, we are
// conservative and disallow the move.
// we can't move I1 across it.
- if (MI.isDebugValue()) {
+ if (MI.isDebugInstr()) {
if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
DbgMItoMove.push_back(&MI);
continue;
@@ -396,7 +396,7 @@
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
DenseMap<unsigned, MachineInstr *> LastDef;
for (MachineInstr &MI : BB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
// Mark TFRs that feed a potential new value store as such.
@@ -423,7 +423,7 @@
MachineBasicBlock::iterator It(DefInst);
unsigned NumInstsToDef = 0;
while (&*It != &MI) {
- if (!It->isDebugValue())
+ if (!It->isDebugInstr())
++NumInstsToDef;
++It;
}
@@ -489,7 +489,7 @@
MI != End;) {
MachineInstr &I1 = *MI++;
- if (I1.isDebugValue())
+ if (I1.isDebugInstr())
continue;
// Don't combine a TFR whose user could be newified (instructions that
@@ -526,7 +526,7 @@
bool &DoInsertAtI1,
bool AllowC64) {
MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
- while (I2 != I1.getParent()->end() && I2->isDebugValue())
+ while (I2 != I1.getParent()->end() && I2->isDebugInstr())
++I2;
unsigned I1DestReg = I1.getOperand(0).getReg();
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 660466d..bbd06ff 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -367,7 +367,7 @@
return false;
for (auto &MI : *B) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
if (MI.isConditionalBranch())
return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index 7c91412..e5af964 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -356,7 +356,7 @@
return false;
};
for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// This isn't 100% accurate, but it's safe.
// It won't detect (as a kill) a case like this
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 78e8257..1ec1ce0 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -134,7 +134,7 @@
MachineBasicBlock::const_instr_iterator MIE) {
unsigned Count = 0;
for (; MIB != MIE; ++MIB) {
- if (!MIB->isDebugValue())
+ if (!MIB->isDebugInstr())
++Count;
}
return Count;
@@ -419,7 +419,7 @@
I = MBB.instr_end();
--I;
- while (I->isDebugValue()) {
+ while (I->isDebugInstr()) {
if (I == MBB.instr_begin())
return false;
--I;
@@ -562,7 +562,7 @@
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Only removing branches from end of MBB.
if (!I->isBranch())
@@ -1626,7 +1626,7 @@
// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return false;
// Throwing call is a boundary.
@@ -3164,7 +3164,7 @@
I = MBB.instr_end();
--I;
- while (I->isDebugValue()) {
+ while (I->isDebugInstr()) {
if (I == MBB.instr_begin())
return Jumpers;
--I;
@@ -4201,7 +4201,7 @@
// use a constant extender, which requires another 4 bytes.
// For debug instructions and prolog labels, return 0.
unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
- if (MI.isDebugValue() || MI.isPosition())
+ if (MI.isDebugInstr() || MI.isPosition())
return 0;
unsigned Size = MI.getDesc().getSize();
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index a3686c8..3dace16 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -302,7 +302,7 @@
// and satisfy the following conditions.
++II;
for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
- if (localII->isDebugValue())
+ if (localII->isDebugInstr())
continue;
// Check 1.
@@ -494,7 +494,7 @@
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
MII != E;) {
MachineInstr &MI = *--MII;
- if (MI.isDebugValue()) {
+ if (MI.isDebugInstr()) {
continue;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 4979ce1..386e6cb 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -163,7 +163,7 @@
if (MI->mayLoad() || MI->mayStore())
if (MemRefsFixed || isVolatileInstr(MI))
return true;
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
return false;
unsigned Opc = MI->getOpcode();
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 8c528b9..2ae48e3 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1037,7 +1037,7 @@
// Ignore bundling of pseudo instructions.
bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
const MachineBasicBlock *) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return true;
if (MI.isCFIInstruction())
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index ceb4887..3d1ec31 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -893,7 +893,7 @@
NodeAddr<BlockNode*> BA = newBlock(Func, &B);
BlockNodes.insert(std::make_pair(&B, BA));
for (MachineInstr &I : B) {
- if (I.isDebugValue())
+ if (I.isDebugInstr())
continue;
buildStmt(BA, I);
}
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index ef50a53..c257d75 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -880,7 +880,7 @@
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
MachineInstr *MI = &*I;
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
continue;
MI->clearKillInfo();
diff --git a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
index 6b4fa77..ea76a11 100644
--- a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
@@ -156,7 +156,7 @@
for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
I != MBB.instr_rend(); ++I) {
// skip debug value
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Convert to forward iterator.
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index a7c9a7a..493d02b 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -573,8 +573,8 @@
while (Instruction != MBB.begin()) {
--Instruction;
- // Skip over debug values.
- if (Instruction->isDebugValue())
+ // Skip over debug instructions.
+ if (Instruction->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator
@@ -699,7 +699,7 @@
while (Instruction != MBB.begin()) {
--Instruction;
- if (Instruction->isDebugValue())
+ if (Instruction->isDebugInstr())
continue;
if (Instruction->getOpcode() != Lanai::BT &&
Instruction->getOpcode() != Lanai::BRCC) {
diff --git a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp
index c29c933..35e2542 100644
--- a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp
+++ b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp
@@ -343,7 +343,7 @@
break;
// Skip over debug instructions
- if (First->isDebugValue())
+ if (First->isDebugInstr())
continue;
if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) {
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
index 6135ce0..dd1b30a 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -113,7 +113,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (I->getOpcode() != MSP430::JMP &&
I->getOpcode() != MSP430::JCC &&
@@ -183,7 +183,7 @@
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 97bb5fb..8ffc073 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -160,6 +160,8 @@
PrintDebugValueComment(MI, OS);
return;
}
+ if (MI->isDebugLabel())
+ return;
// If we just ended a constant pool, mark it as such.
if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
index 5e7a1af..5ee816b 100644
--- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -661,7 +661,7 @@
if (!BBHasFallthrough(&MBB))
WaterList.push_back(&MBB);
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
int Opc = MI.getOpcode();
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 4f292e6..dfebc343 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -679,7 +679,7 @@
++I;
// skip debug value
- if (CurrI->isDebugValue())
+ if (CurrI->isDebugInstr())
continue;
if (terminateSearch(*CurrI))
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 947d7e4..9254ae6 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -163,7 +163,7 @@
// Note that indirect branches are not removed.
while (I != REnd && removed < 2) {
// Skip past debug instructions.
- if (I->isDebugValue()) {
+ if (I->isDebugInstr()) {
++I;
continue;
}
@@ -195,7 +195,7 @@
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
// Skip all the debug instructions.
- while (I != REnd && I->isDebugValue())
+ while (I != REnd && I->isDebugInstr())
++I;
if (I == REnd || !isUnpredicatedTerminator(*I)) {
@@ -220,7 +220,7 @@
// Skip past any debug instruction to see if the second last actual
// is a branch.
++I;
- while (I != REnd && I->isDebugValue())
+ while (I != REnd && I->isDebugInstr())
++I;
if (I != REnd) {
diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp
index bc5f0df..7a7c8ab 100644
--- a/llvm/lib/Target/Mips/MipsLongBranch.cpp
+++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp
@@ -125,7 +125,7 @@
// found or it reaches E.
static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
for (; B != E; ++B)
- if (!B->isDebugValue())
+ if (!B->isDebugInstr())
return B;
return E;
diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
index 1699463..ed5e496 100644
--- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -128,7 +128,7 @@
if (J->getOperand(i).isMBB() &&
J->getOperand(i).getMBB() == &ReturnMBB)
OtherReference = true;
- } else if (!J->isTerminator() && !J->isDebugValue())
+ } else if (!J->isTerminator() && !J->isDebugInstr())
break;
if (J == (*PI)->begin())
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index f327396..4c718f8 100644
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -330,7 +330,7 @@
MachineInstr *MI = SU->getInstr();
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
return NoHazard;
unsigned Opcode = MI->getOpcode();
@@ -388,7 +388,7 @@
void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
MachineInstr *MI = SU->getInstr();
- if (MI->isDebugValue())
+ if (MI->isDebugInstr())
return;
unsigned Opcode = MI->getOpcode();
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 8151e43..6f44e3a 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -232,7 +232,7 @@
SomethingChanged = false;
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
if (TII->convertToImmediateForm(MI)) {
@@ -261,7 +261,7 @@
}
// Ignore debug instructions.
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
// Per-opcode peepholes.
diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index 635f8cd..83c9dd6 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -249,7 +249,7 @@
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
bool RelevantInstr = false;
diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
index 9b1d0f5..6290e5a 100644
--- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -207,8 +207,8 @@
if (!done)
--I;
- // skip debug value
- if (I->isDebugValue())
+ // skip debug instruction
+ if (I->isDebugInstr())
continue;
if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index ea8ed83..6750763 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -280,7 +280,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (I->getOpcode() != SP::BA
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index f094cf1..f0f9211 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -389,7 +389,7 @@
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator instruction, we're
@@ -479,7 +479,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (!I->isBranch())
break;
diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
index ef8b980..802962b 100644
--- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -295,7 +295,7 @@
// Add the terminators.
while (MI != End) {
- if (!MI->isDebugValue()) {
+ if (!MI->isDebugInstr()) {
assert(MI->isTerminator() && "Terminator followed by non-terminator");
Terminators.push_back(describeTerminator(*MI));
skipTerminator(Position, Terminators.back(), false);
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index 51e8beb..1de11a1 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -65,7 +65,7 @@
std::next(LastEmittedMI) : MBB->begin());
for (; I != NextBegin; ++I) {
- if (I->isPosition() || I->isDebugValue())
+ if (I->isPosition() || I->isDebugInstr())
continue;
HazardRec->emitInstruction(&*I);
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
index cf1bbfa..3429c4f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
@@ -265,7 +265,7 @@
for (MachineBasicBlock &MBB : reverse(MF)) {
for (MachineInstr &MI : reverse(MBB)) {
- if (MI.isPosition() || MI.isDebugValue())
+ if (MI.isPosition() || MI.isDebugInstr())
continue;
if (MI.getOpcode() == WebAssembly::END_BLOCK) {
BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
index cf14643..caf12a6 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
@@ -231,7 +231,7 @@
MachineInstr &MI = *I++;
assert(!WebAssembly::isArgument(MI));
- if (MI.isDebugValue() || MI.isLabel())
+ if (MI.isDebugInstr() || MI.isLabel())
continue;
// Replace tee instructions with tee_local. The difference is that tee
@@ -375,7 +375,7 @@
// Assert that all registers have been stackified at this point.
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
- if (MI.isDebugValue() || MI.isLabel())
+ if (MI.isDebugInstr() || MI.isLabel())
continue;
for (const MachineOperand &MO : MI.explicit_operands()) {
assert(
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index 739d6cf..fbdf4c0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -151,7 +151,7 @@
while (I != MBB.instr_begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (!I->isTerminator())
break;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 6780f25..c326bdb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -163,7 +163,7 @@
assert(!MI.isPosition());
assert(!MI.isTerminator());
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
return;
// Check for loads.
@@ -871,7 +871,7 @@
SmallVector<unsigned, 0> Stack;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
for (MachineOperand &MO : reverse(MI.explicit_operands())) {
if (!MO.isReg())
diff --git a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
index 522dc79..c73fd6e 100644
--- a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
+++ b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
@@ -375,7 +375,7 @@
// Skip over DEBUG_VALUE.
// For globals in PIC mode, we can have some LEAs here. Skip them as well.
// TODO: Extend this to something that covers more cases.
- while (I->getOpcode() == X86::LEA32r || I->isDebugValue())
+ while (I->getOpcode() == X86::LEA32r || I->isDebugInstr())
++I;
unsigned StackPtr = RegInfo.getStackRegister();
diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp
index 493d42c..38baa90 100644
--- a/llvm/lib/Target/X86/X86CmovConversion.cpp
+++ b/llvm/lib/Target/X86/X86CmovConversion.cpp
@@ -295,7 +295,7 @@
for (auto &I : *MBB) {
// Skip debug instructions.
- if (I.isDebugValue())
+ if (I.isDebugInstr())
continue;
X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode());
// Check if we found a X86::CMOVrr instruction.
@@ -435,7 +435,7 @@
RegDefMaps[PhyRegType].clear();
for (MachineInstr &MI : *MBB) {
// Skip debug instructions.
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
unsigned MIDepth = 0;
unsigned MIDepthOpt = 0;
@@ -605,7 +605,7 @@
SmallVector<MachineInstr *, 2> DBGInstructions;
for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) {
- if (I->isDebugValue())
+ if (I->isDebugInstr())
DBGInstructions.push_back(&*I);
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 248f960..ffdb949 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1675,7 +1675,7 @@
for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
std::bitset<8> Defs;
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 42f9676..18f62e0 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -3025,7 +3025,7 @@
// Count the number of uses for each object.
for (auto &MBB : MF) {
for (auto &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
for (const MachineOperand &MO : MI.operands()) {
// Check to see if it's a local stack symbol.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 203c131..16ee56e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27766,7 +27766,7 @@
MCSymbol *Sym = nullptr;
for (const auto &MI : MBB) {
- if (MI.isDebugValue())
+ if (MI.isDebugInstr())
continue;
assert(MI.isEHLabel() && "expected EH_LABEL");
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5c85c7e..31ce4bd 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4340,8 +4340,8 @@
// This instruction defines EFLAGS, no need to look any further.
return true;
++Iter;
- // Skip over DBG_VALUE.
- while (Iter != E && Iter->isDebugValue())
+ // Skip over debug instructions.
+ while (Iter != E && Iter->isDebugInstr())
++Iter;
}
@@ -4363,8 +4363,8 @@
return !MBB.isLiveIn(X86::EFLAGS);
--Iter;
- // Skip over DBG_VALUE.
- while (Iter != B && Iter->isDebugValue())
+ // Skip over debug instructions.
+ while (Iter != B && Iter->isDebugInstr())
--Iter;
bool SawKill = false;
@@ -6254,7 +6254,7 @@
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (!I->isBranch())
assert(0 && "Can't find the branch to replace!");
@@ -6322,7 +6322,7 @@
MachineBasicBlock::iterator UnCondBrIter = MBB.end();
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator instruction, we're
@@ -6559,7 +6559,7 @@
while (I != MBB.begin()) {
--I;
- if (I->isDebugValue())
+ if (I->isDebugInstr())
continue;
if (I->getOpcode() != X86::JMP_1 &&
X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
@@ -11172,7 +11172,7 @@
X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
MachineInstr &MI = *MIT;
// Don't allow debug values to impact outlining type.
- if (MI.isDebugValue() || MI.isIndirectDebugValue())
+ if (MI.isDebugInstr() || MI.isIndirectDebugValue())
return MachineOutlinerInstrType::Invisible;
// At this point, KILL instructions don't really tell us much so we can go
diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp
index 2fe5cb9..85b9aec 100644
--- a/llvm/lib/Target/X86/X86PadShortFunction.cpp
+++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp
@@ -129,7 +129,7 @@
"Basic block should contain at least a RET but is empty");
MachineBasicBlock::iterator ReturnLoc = --MBB->end();
- while (ReturnLoc->isDebugValue())
+ while (ReturnLoc->isDebugInstr())
--ReturnLoc;
assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() &&
"Basic block does not end with RET");
diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
index a5fe63b..b87c149 100644
--- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
@@ -427,7 +427,7 @@
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
DebugLoc DL;
- if (MI != MBB.end() && !MI->isDebugValue())
+ if (MI != MBB.end() && !MI->isDebugInstr())
DL = MI->getDebugLoc();
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index c885332..d5e2767 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -364,7 +364,7 @@
const TargetRegisterInfo *TRI) const
{
DebugLoc DL;
- if (I != MBB.end() && !I->isDebugValue())
+ if (I != MBB.end() && !I->isDebugInstr())
DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();
@@ -386,7 +386,7 @@
const TargetRegisterInfo *TRI) const
{
DebugLoc DL;
- if (I != MBB.end() && !I->isDebugValue())
+ if (I != MBB.end() && !I->isDebugInstr())
DL = I->getDebugLoc();
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();
@@ -429,7 +429,7 @@
MachineBasicBlock::iterator MI,
unsigned Reg, uint64_t Value) const {
DebugLoc dl;
- if (MI != MBB.end() && !MI->isDebugValue())
+ if (MI != MBB.end() && !MI->isDebugInstr())
dl = MI->getDebugLoc();
if (isImmMskBitp(Value)) {
int N = Log2_32(Value) + 1;