[SelectionDAG] Add support for vector demandedelts in BSWAP opcodes
llvm-svn: 286582
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index eee4cda..7a9dd57 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2575,7 +2575,8 @@
break;
}
case ISD::BSWAP: {
- computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
+ computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
+ Depth + 1);
KnownZero = KnownZero2.byteSwap();
KnownOne = KnownOne2.byteSwap();
break;
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll
index 0cdd1f3..068894b 100644
--- a/llvm/test/CodeGen/X86/known-bits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-bits-vector.ll
@@ -309,16 +309,12 @@
define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_bswap_shuffle_shl:
; X32: # BB#0:
-; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,3,2,1,0,15,14,13,12,15,14,13,12]
-; X32-NEXT: vpslld $22, %xmm0, %xmm0
+; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_bswap_shuffle_shl:
; X64: # BB#0:
-; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,3,2,1,0,15,14,13,12,15,14,13,12]
-; X64-NEXT: vpslld $22, %xmm0, %xmm0
+; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>
%2 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %1)