[SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used. Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.
This particularly helps with llvmpipe.
Based on a patch by Richard Sandiford.
llvm-svn: 236523
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-01.ll b/llvm/test/CodeGen/SystemZ/vec-move-01.ll
index f9ae13b..896d24a 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-01.ll
@@ -34,6 +34,14 @@
ret <2 x i64> %val2
}
+; Test v4f32 moves.
+define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f5:
+; CHECK: vlr %v24, %v26
+; CHECK: br %r14
+ ret <4 x float> %val2
+}
+
; Test v2f64 moves.
define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) {
; CHECK-LABEL: f6: