[SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used. Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.
This particularly helps with llvmpipe.
Based on a patch by Richard Sandiford.
llvm-svn: 236523
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-13.ll b/llvm/test/CodeGen/SystemZ/vec-move-13.ll
index c50c94a..4ad8e3f 100644
--- a/llvm/test/CodeGen/SystemZ/vec-move-13.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-move-13.ll
@@ -46,6 +46,17 @@
ret <2 x i64> %ret
}
+; Test v4f32 insertion into 0.
+define <4 x float> @f5(float %val) {
+; CHECK-LABEL: f5:
+; CHECK: vgbm [[ZERO:%v[0-9]+]], 0
+; CHECK: vmrhf [[REG:%v[0-9]+]], [[ZERO]], %v0
+; CHECK: vmrhg %v24, [[ZERO]], [[REG]]
+; CHECK: br %r14
+ %ret = insertelement <4 x float> zeroinitializer, float %val, i32 3
+ ret <4 x float> %ret
+}
+
; Test v2f64 insertion into 0.
define <2 x double> @f6(double %val) {
; CHECK-LABEL: f6:
@@ -55,3 +66,4 @@
%ret = insertelement <2 x double> zeroinitializer, double %val, i32 1
ret <2 x double> %ret
}
+