[SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used. Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.
This particularly helps with llvmpipe.
Based on a patch by Richard Sandiford.
llvm-svn: 236523
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-06.ll b/llvm/test/CodeGen/SystemZ/vec-perm-06.ll
index 298fc60..835276a 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-06.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-06.ll
@@ -138,3 +138,23 @@
<4 x i32> <i32 5, i32 7, i32 1, i32 3>
ret <4 x i32> %ret
}
+
+; Test a canonical v4f32 pack.
+define <4 x float> @f12(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f12:
+; CHECK: vpkg %v24, %v24, %v26
+; CHECK: br %r14
+ %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+ <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x float> %ret
+}
+
+; Test a reversed v4f32 pack.
+define <4 x float> @f13(<4 x float> %val1, <4 x float> %val2) {
+; CHECK-LABEL: f13:
+; CHECK: vpkg %v24, %v26, %v24
+; CHECK: br %r14
+ %ret = shufflevector <4 x float> %val1, <4 x float> %val2,
+ <4 x i32> <i32 5, i32 7, i32 1, i32 3>
+ ret <4 x float> %ret
+}