commit 80e66ce0b453cb08da6bc54e7148b8048c3b4b02
author Andrew Trick <atrick@apple.com> Fri Apr 05 00:31:34 2013 +0000
committer Andrew Trick <atrick@apple.com> Fri Apr 05 00:31:34 2013 +0000
tree c53c216d7031741d07381c3d340f0167efc4a81d
parent 96ce3848d6dcd1ae6c042a63c35012ec22c1a63f

RegisterPressure heuristics currently require signed comparisons.

llvm-svn: 178823

llvm/lib/CodeGen/MachineScheduler.cpp

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index ed6b986..5bd2349 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1660,7 +1660,7 @@
 }
 
 /// Return true if this heuristic determines order.
-static bool tryLess(unsigned TryVal, unsigned CandVal,
+static bool tryLess(int TryVal, int CandVal,
                     ConvergingScheduler::SchedCandidate &TryCand,
                     ConvergingScheduler::SchedCandidate &Cand,
                     ConvergingScheduler::CandReason Reason) {
@@ -1676,7 +1676,7 @@
   return false;
 }
 
-static bool tryGreater(unsigned TryVal, unsigned CandVal,
+static bool tryGreater(int TryVal, int CandVal,
                        ConvergingScheduler::SchedCandidate &TryCand,
                        ConvergingScheduler::SchedCandidate &Cand,
                        ConvergingScheduler::CandReason Reason) {