[SystemZ] Support z15 processor name
The recently announced IBM z15 processor implements the architecture
already supported as "arch13" in LLVM. This patch adds support for
"z15" as an alternate architecture name for arch13.
The patch also uses z15 in a number of places where we used arch13
as long as the official name was not yet announced.
llvm-svn: 372435
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index 0d6fab5..5509ec0 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -316,7 +316,7 @@
unsigned int Id;
if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
if (Id >= 8561 && HaveVectorSupport)
- return "arch13";
+ return "z15";
if (Id >= 3906 && HaveVectorSupport)
return "z14";
if (Id >= 2964 && HaveVectorSupport)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index aaf7c58..6a0f59e 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -258,7 +258,7 @@
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
- // On arch13 we have native support for a 64-bit CTPOP.
+ // On z15 we have native support for a 64-bit CTPOP.
if (Subtarget.hasMiscellaneousExtensions3()) {
setOperationAction(ISD::CTPOP, MVT::i32, Promote);
setOperationAction(ISD::CTPOP, MVT::i64, Legal);
diff --git a/llvm/lib/Target/SystemZ/SystemZProcessors.td b/llvm/lib/Target/SystemZ/SystemZProcessors.td
index b27c25b..af33a03 100644
--- a/llvm/lib/Target/SystemZ/SystemZProcessors.td
+++ b/llvm/lib/Target/SystemZ/SystemZProcessors.td
@@ -35,5 +35,6 @@
def : ProcessorModel<"arch12", Z14Model, Arch12SupportedFeatures.List>;
def : ProcessorModel<"z14", Z14Model, Arch12SupportedFeatures.List>;
-def : ProcessorModel<"arch13", Arch13Model, Arch13SupportedFeatures.List>;
+def : ProcessorModel<"arch13", Z15Model, Arch13SupportedFeatures.List>;
+def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
diff --git a/llvm/lib/Target/SystemZ/SystemZSchedule.td b/llvm/lib/Target/SystemZ/SystemZSchedule.td
index 98eca28..119e3ee 100644
--- a/llvm/lib/Target/SystemZ/SystemZSchedule.td
+++ b/llvm/lib/Target/SystemZ/SystemZSchedule.td
@@ -59,7 +59,7 @@
def MCD : SchedWrite; // Millicode
-include "SystemZScheduleArch13.td"
+include "SystemZScheduleZ15.td"
include "SystemZScheduleZ14.td"
include "SystemZScheduleZ13.td"
include "SystemZScheduleZEC12.td"
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleArch13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
similarity index 97%
rename from llvm/lib/Target/SystemZ/SystemZScheduleArch13.td
rename to llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 9f82f24..56ceb88 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleArch13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -1,4 +1,4 @@
-//-- SystemZScheduleArch13.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
+//-- SystemZScheduleZ15.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,14 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines the machine model for Arch13 to support instruction
+// This file defines the machine model for Z15 to support instruction
// scheduling and other instruction cost heuristics.
//
// Pseudos expanded right after isel do not need to be modelled here.
//
//===----------------------------------------------------------------------===//
-def Arch13Model : SchedMachineModel {
+def Z15Model : SchedMachineModel {
let UnsupportedFeatures = Arch13UnsupportedFeatures.List;
@@ -27,7 +27,7 @@
let MispredictPenalty = 20;
}
-let SchedModel = Arch13Model in {
+let SchedModel = Z15Model in {
// These definitions need the SchedModel value. They could be put in a
// subtarget common include file, but it seems the include system in Tablegen
// currently (2016) rejects multiple includes of same file.
@@ -73,43 +73,43 @@
}
// Execution units.
-def Arch13_FXaUnit : ProcResource<2>;
-def Arch13_FXbUnit : ProcResource<2>;
-def Arch13_LSUnit : ProcResource<2>;
-def Arch13_VecUnit : ProcResource<2>;
-def Arch13_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ }
-def Arch13_VBUnit : ProcResource<2>;
-def Arch13_MCD : ProcResource<1>;
+def Z15_FXaUnit : ProcResource<2>;
+def Z15_FXbUnit : ProcResource<2>;
+def Z15_LSUnit : ProcResource<2>;
+def Z15_VecUnit : ProcResource<2>;
+def Z15_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ }
+def Z15_VBUnit : ProcResource<2>;
+def Z15_MCD : ProcResource<1>;
// Subtarget specific definitions of scheduling resources.
let NumMicroOps = 0 in {
- def : WriteRes<FXa, [Arch13_FXaUnit]>;
- def : WriteRes<FXb, [Arch13_FXbUnit]>;
- def : WriteRes<LSU, [Arch13_LSUnit]>;
- def : WriteRes<VecBF, [Arch13_VecUnit]>;
- def : WriteRes<VecDF, [Arch13_VecUnit]>;
- def : WriteRes<VecDFX, [Arch13_VecUnit]>;
- def : WriteRes<VecMul, [Arch13_VecUnit]>;
- def : WriteRes<VecStr, [Arch13_VecUnit]>;
- def : WriteRes<VecXsPm, [Arch13_VecUnit]>;
+ def : WriteRes<FXa, [Z15_FXaUnit]>;
+ def : WriteRes<FXb, [Z15_FXbUnit]>;
+ def : WriteRes<LSU, [Z15_LSUnit]>;
+ def : WriteRes<VecBF, [Z15_VecUnit]>;
+ def : WriteRes<VecDF, [Z15_VecUnit]>;
+ def : WriteRes<VecDFX, [Z15_VecUnit]>;
+ def : WriteRes<VecMul, [Z15_VecUnit]>;
+ def : WriteRes<VecStr, [Z15_VecUnit]>;
+ def : WriteRes<VecXsPm, [Z15_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
- def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Arch13_FXaUnit]>;
- def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Arch13_FXbUnit]>;
- def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Arch13_LSUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Arch13_VecUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Arch13_VecUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Arch13_VecUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Arch13_VecUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Arch13_VecUnit]>;
- def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Arch13_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
+ def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
+ def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z15_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z15_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z15_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z15_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z15_VecUnit]>;
+ def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
}}
- def : WriteRes<VecFPd, [Arch13_VecFPdUnit]> { let ResourceCycles = [30]; }
+ def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
- def : WriteRes<VBU, [Arch13_VBUnit]>; // Virtual Branching Unit
+ def : WriteRes<VBU, [Z15_VBUnit]>; // Virtual Branching Unit
}
-def : WriteRes<MCD, [Arch13_MCD]> { let NumMicroOps = 3;
+def : WriteRes<MCD, [Z15_MCD]> { let NumMicroOps = 3;
let BeginGroup = 1;
let EndGroup = 1; }
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 145cf87..8d45e67 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -707,7 +707,7 @@
// TODO: Fix base implementation which could simplify things a bit here
// (seems to miss on differentiating on scalar/vector types).
- // Only 64 bit vector conversions are natively supported before arch13.
+ // Only 64 bit vector conversions are natively supported before z15.
if (DstScalarBits == 64 || ST->hasVectorEnhancements2()) {
if (SrcScalarBits == DstScalarBits)
return NumDstVectors;