commit 8275f0e0af03f1950cc60e070aacf15389b81fcf
author Evan Cheng <evan.cheng@apple.com> Mon Mar 26 07:12:51 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Mar 26 07:12:51 2007 +0000
tree 95a26b9c593a8e90ce48efead8331a41a61ae739
parent 0bfa19eb131d80498a30880c537373c74202a4b4

SIGN_EXTEND_INREG requires one extra operand, a ValueType node.

llvm-svn: 35350

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6187aba..8f90521 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2327,8 +2327,12 @@
       CombineTo(N->getOperand(0).Val, Load);
     } else
       CombineTo(N0.Val, Load, Load.getValue(1));
-    if (ShAmt)
-      return DAG.getNode(N->getOpcode(), VT, Load);
+    if (ShAmt) {
+      if (Opc == ISD::SIGN_EXTEND_INREG)
+        return DAG.getNode(Opc, VT, Load, N->getOperand(1));
+      else
+        return DAG.getNode(Opc, VT, Load);
+    }
     return SDOperand(N, 0);   // Return N so it doesn't get rechecked!
   }