commit 82e5e1e564d77dcd8babbfa9c2850912f94786e4
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 15 21:27:08 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 15 21:27:08 2016 +0000
tree 81e53dcf93d1effa226d94c94967d4646f2cbcaa
parent 11d3e21f2b7297ddcb213f6892134b5c8f2a520b

AMDGPU: Fix TargetPrefix for remaining r600 intrinsics

llvm-svn: 275619

llvm/test/CodeGen/AMDGPU/input-mods.ll

diff --git a/llvm/test/CodeGen/AMDGPU/input-mods.ll b/llvm/test/CodeGen/AMDGPU/input-mods.ll
index c098d23..720790d 100644
--- a/llvm/test/CodeGen/AMDGPU/input-mods.ll
+++ b/llvm/test/CodeGen/AMDGPU/input-mods.ll
@@ -15,10 +15,10 @@
    %r2 = fsub float -0.000000e+00, %r1
    %r3 = call float @llvm.exp2.f32(float %r2)
    %vec = insertelement <4 x float> undef, float %r3, i32 0
-   call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
+   call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
    ret void
 }
 
 declare float @llvm.exp2.f32(float) readnone
 declare float @llvm.fabs.f32(float) readnone
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)