AMDGPU: Fix TargetPrefix for remaining r600 intrinsics
llvm-svn: 275619
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
index b2450a9..78b8812 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll
@@ -39,7 +39,7 @@
%tmp29 = insertelement <4 x float> %tmp28, float %tmp25, i32 3
%tmp30 = shufflevector <4 x float> %tmp29, <4 x float> %tmp29, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp31 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp30, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1)
- call void @llvm.R600.store.swizzle(<4 x float> %tmp31, i32 0, i32 0)
+ call void @llvm.r600.store.swizzle(<4 x float> %tmp31, i32 0, i32 0)
ret void
}
@@ -49,7 +49,7 @@
; Function Attrs: nounwind readnone
declare float @llvm.fabs.f32(float) #0
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
; Function Attrs: readnone
declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0