commit 82e5e1e564d77dcd8babbfa9c2850912f94786e4
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 15 21:27:08 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 15 21:27:08 2016 +0000
tree 81e53dcf93d1effa226d94c94967d4646f2cbcaa
parent 11d3e21f2b7297ddcb213f6892134b5c8f2a520b

AMDGPU: Fix TargetPrefix for remaining r600 intrinsics

llvm-svn: 275619

llvm/test/CodeGen/AMDGPU/schedule-if.ll

diff --git a/llvm/test/CodeGen/AMDGPU/schedule-if.ll b/llvm/test/CodeGen/AMDGPU/schedule-if.ll
index 94c653c..6637b38 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-if.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-if.ll
@@ -32,7 +32,7 @@
   %17 = insertelement <4 x float> %16, float %temp1.0, i32 1
   %18 = insertelement <4 x float> %17, float 0.000000e+00, i32 2
   %19 = insertelement <4 x float> %18, float %temp3.0, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
+  call void @llvm.r600.store.swizzle(<4 x float> %19, i32 0, i32 0)
   ret void
 
 IF13:                                             ; preds = %ELSE
@@ -43,4 +43,4 @@
   br label %ENDIF
 }
 
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)