commit 82f364515c525bff550f741c52a2479581effc77
author Andrew Lenharth <andrewl@lenharth.org> Wed Mar 23 15:20:01 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Wed Mar 23 15:20:01 2005 +0000
tree 966670df547ad1ffef469e6f3654b591f404d25f
parent e36d77b7264ad838a619cc86fbf4c9b8cb42abed

don't lie to the register allocator

llvm-svn: 20784

llvm/lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index d25c36e..abf9934 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1068,7 +1068,7 @@
         unsigned Tmp9 = MakeReg(MVT::f64);
         
         BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxL).addReg(Alpha::F31);
-        BuildMI(BB, Alpha::STQ, 3).addReg(Tmp1).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::STQ, 3).addReg(Tmp2).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
         BuildMI(BB, Alpha::LDT, 2, Tmp4).addFrameIndex(FrameIdxL).addReg(Alpha::F31);
         BuildMI(BB, Alpha::LDT, 2, Tmp5).addFrameIndex(FrameIdxR).addReg(Alpha::F31);
         BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4);
@@ -1076,7 +1076,7 @@
         BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7);
         BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8);
         BuildMI(BB, Alpha::STT, 3).addReg(Tmp9).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
-        BuildMI(BB, Alpha::LDQ, 3).addReg(Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
+        BuildMI(BB, Alpha::LDQ, 2, Result).addFrameIndex(FrameIdxF).addReg(Alpha::F31);
         return Result;
       }