Iterate over phys regs instead
llvm-svn: 255816
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
index e853b76..084c4ed 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
@@ -91,7 +91,10 @@
//===----------------------------------------------------------------------===//
MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
- const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
+ const TargetRegisterClass *TRC =
+ TargetRegisterInfo::isVirtualRegister(RegNo) ?
+ MRI->getRegClass(RegNo) :
+ MRI->getTargetRegisterInfo()->getMinimalPhysRegClass(RegNo);
for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
if (TRC->hasType(T))
return T;
@@ -182,9 +185,11 @@
Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy));
AnyWARegs = true;
}
- if (MF->getFrameInfo()->getStackSize() > 0) {
- // TODO: wasm64
- Local.addOperand(MCOperand::createImm(MVT::i32));
+ auto &PhysRegs = MFI->getPhysRegs();
+ for (unsigned PReg = 0; PReg < PhysRegs.size(); ++PReg) {
+ if (PhysRegs[PReg] == -1U)
+ continue;
+ Local.addOperand(MCOperand::createImm(getRegType(PReg).SimpleTy));
AnyWARegs = true;
}
if (AnyWARegs)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
index e3c7f41..6a60280 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
@@ -89,6 +89,7 @@
assert(WAReg < -1U);
PhysRegs[PReg] = WAReg;
}
+ const std::vector<unsigned> &getPhysRegs() const { return PhysRegs; }
};
} // end namespace llvm