commit 83a2a62fb47f1beeef62eed5bdba4a2480eb3da9
author Sjoerd Meijer <sjoerd.meijer@arm.com> Thu Jul 12 14:57:59 2018 +0000
committer Sjoerd Meijer <sjoerd.meijer@arm.com> Thu Jul 12 14:57:59 2018 +0000
tree 06e5c5fb6073687d31cb05be0089d1cbe6e72d5e
parent 733a8d6886ee0380007c77c0b7d2dbbba64a0272

[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions

These instructions are added to AArch64 only.

llvm-svn: 336913

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 5089f1e..ff3e0ca 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1183,6 +1183,14 @@
   case AArch64::LDRHHpost:
   case AArch64::STRWpost:
   case AArch64::LDRWpost:
+  case AArch64::STLURBi:
+  case AArch64::STLURHi:
+  case AArch64::STLURi:
+  case AArch64::LDAPURBi:
+  case AArch64::LDAPURSBi:
+  case AArch64::LDAPURHi:
+  case AArch64::LDAPURSHi:
+  case AArch64::LDAPURi:
     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURSBXi:
@@ -1205,6 +1213,11 @@
   case AArch64::STRXpost:
   case AArch64::LDRSWpost:
   case AArch64::LDRXpost:
+  case AArch64::LDAPURSWi:
+  case AArch64::LDAPURSH64i:
+  case AArch64::LDAPURSB64i:
+  case AArch64::STLUR64i:
+  case AArch64::LDAPUR64i:
     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURQi: