X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
linked together).
llvm-svn: 25247
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8b15727..321a9c3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -161,8 +161,8 @@
if (X86ScalarSSE) {
// Set up the FP register classes.
- addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
- addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
+ addRegisterClass(MVT::f32, X86::FR32RegisterClass);
+ addRegisterClass(MVT::f64, X86::FR64RegisterClass);
// SSE has no load+extend ops
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index d6dc20a..990faf6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -74,7 +74,8 @@
[SDNPOutFlag]>;
def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
[SDNPHasChain]>;
-def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>;
+def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
+ [SDNPOutFlag]>;
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
[SDNPHasChain, SDNPOptInFlag]>;