[SystemZ] Use zeroing form of RISBG for some AND sequences

RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.

It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.

llvm-svn: 186072
diff --git a/llvm/test/CodeGen/SystemZ/fp-move-02.ll b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
index c2bb931..a02c856 100644
--- a/llvm/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
@@ -39,9 +39,9 @@
 define float @f4(i64 %big) {
 ; CHECK: f4:
 ; CHECK-NOT: %r2
-; CHECK: nilf %r2, 0
-; CHECK-NOT: %r2
-; CHECK: ldgr %f0, %r2
+; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
+; CHECK-NOT: [[REG]]
+; CHECK: ldgr %f0, [[REG]]
   %shift = ashr i64 %big, 32
   %a = trunc i64 %shift to i32
   %res = bitcast i32 %a to float