Add mfrtcu and mfrtcl instructions
llvm-svn: 215109
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 646d2670..aa5466c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3226,6 +3226,9 @@
def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
+def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
+def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
+
def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
index c23ef8f..0729154 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -3419,6 +3419,12 @@
# CHECK-BE: mfspr 2, 1 # encoding: [0x7c,0x41,0x02,0xa6]
# CHECK-LE: mfspr 2, 1 # encoding: [0xa6,0x02,0x41,0x7c]
mfxer 2
+# CHECK-BE: mfspr 2, 4 # encoding: [0x7c,0x44,0x02,0xa6]
+# CHECK-LE: mfspr 2, 4 # encoding: [0xa6,0x02,0x44,0x7c]
+ mfrtcu 2
+# CHECK-BE: mfspr 2, 5 # encoding: [0x7c,0x45,0x02,0xa6]
+# CHECK-LE: mfspr 2, 5 # encoding: [0xa6,0x02,0x45,0x7c]
+ mfrtcl 2
# CHECK-BE: mtspr 17, 2 # encoding: [0x7c,0x51,0x03,0xa6]
# CHECK-LE: mtspr 17, 2 # encoding: [0xa6,0x03,0x51,0x7c]
mtdscr 2