| commit | 85f34a56829f79cb377f3d84a5842cef60667ba7 | [log] [tgz] |
|---|---|---|
| author | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 13:55:53 2005 +0000 |
| committer | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 13:55:53 2005 +0000 |
| tree | 238f3ea7a15cd9cc1d61a14137af946435868100 | |
| parent | a7abda39894a8669b4aa05bd35dfced76fa8a3c6 [diff] [blame] |
Yea, it wasn't happy llvm-svn: 21132
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index c3b9c1f..6c3a87a 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1136,6 +1136,7 @@ Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; case ISD::MULHS: { //MULHU - Ra<63>*Rb - Rb<63>*Ra