commit 8610c9f43a386ee40cbfd7addb507434205b2cc4
author Richard Trieu <rtrieu@google.com> Fri Jan 26 21:55:13 2018 +0000
committer Richard Trieu <rtrieu@google.com> Fri Jan 26 21:55:13 2018 +0000
tree 029034165ffc9ccdf28a527f5af58950c70bcf26
parent 90ca4e8b0c2785b03f5a7c29277bab6fd77fc195

Inline variable only used within assert.

llvm-svn: 323569

llvm/lib/Target/Hexagon/HexagonVExtract.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
index 67c201d..929ac2b 100644
--- a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
@@ -140,9 +140,8 @@
 
     for (MachineInstr *ExtI : P.second) {
       assert(ExtI->getOpcode() == Hexagon::V6_extractw);
-      unsigned VR = ExtI->getOperand(1).getReg();
       unsigned SR = ExtI->getOperand(1).getSubReg();
-      assert(VR == VecR);
+      assert(ExtI->getOperand(1).getReg() == VecR);
 
       MachineBasicBlock &ExtB = *ExtI->getParent();
       DebugLoc DL = ExtI->getDebugLoc();