commit 8656a156cfcd33a1638ce9c815d556c667aef4cc
author Nate Begeman <natebegeman@mac.com> Mon Sep 27 05:08:17 2004 +0000
committer Nate Begeman <natebegeman@mac.com> Mon Sep 27 05:08:17 2004 +0000
tree 5174b712339e2c159debc5d2621143e5e1c33d53
parent a68d76ebfa9baa979b5baeadf762c871863cc5fa

Correct some BuildMI arguments for the upcoming simple scheduler

llvm-svn: 16519

llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 057615d..c8fde63 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -557,7 +557,7 @@
     MachineBasicBlock::iterator MBBI = FirstMBB.begin();
     GlobalBaseReg = makeAnotherReg(Type::IntTy);
     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
-    BuildMI(FirstMBB, MBBI, PPC::MFLR, 0, GlobalBaseReg).addReg(PPC::LR);
+    BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
     GlobalBaseInitialized = true;
   }
   // Emit our copy of GlobalBaseReg to the destination register in the

llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp

diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
index 321a449..a7b5cb5 100644
--- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
@@ -78,7 +78,7 @@
 
   unsigned OC = Opcode[getIdx(RC)];
   if (SrcReg == PPC::LR) {
-    BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
+    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
   } else {

llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp

diff --git a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
index 1871c2e..9375c2c 100644
--- a/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
@@ -78,7 +78,7 @@
   const TargetRegisterClass *RC = getRegClass(SrcReg);
   unsigned OC = Opcode[getIdx(RC)];
   if (SrcReg == PPC::LR) {
-    BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
+    BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
     BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
     addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
   } else {