AMDGPU: Fix unnecessary ands when packing f16 vectors
computeKnownBits didn't handle fp_to_fp16 to report
the high bits as 0. ARM maps the generic node to an instruction
that does not modify the high bits of the register, so introduce
a target node where the high bits are known 0.
llvm-svn: 297873
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index a69e21f..050398c 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -188,19 +188,19 @@
; GCN-LABEL: {{^}}select_v2f16_imm_a:
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
-; SI: v_cmp_lt_f32_e32 vcc, 0.5
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e64
+; SI: v_cmp_lt_f32_e32 vcc, 0.5
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
; GCN: v_cndmask_b32_e32
-; SI: v_cvt_f16_f32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
+; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_a(
<2 x half> addrspace(1)* %r,
@@ -220,18 +220,19 @@
; GCN-LABEL: {{^}}select_v2f16_imm_b:
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
-; SI: v_cmp_gt_f32_e32 vcc, 0.5
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_gt_f32_e64
+; SI: v_cmp_gt_f32_e32 vcc, 0.5
; VI: v_cmp_gt_f16_e32
; VI: v_cmp_gt_f16_e64
; GCN: v_cndmask_b32_e32
-; SI: v_cvt_f16_f32_e32
; GCN: v_cndmask_b32_e64
+
+; SI: v_cvt_f16_f32_e32
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_b(
@@ -258,8 +259,8 @@
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_nlt_f32_e32
-; SI: v_cndmask_b32_e32
-; SI: v_cmp_nlt_f32_e32
+; SI: v_cmp_nlt_f32_e64
+; SI: v_cndmask_b32_e64
; SI: v_cndmask_b32_e32
; VI: v_cmp_nlt_f16_e32
@@ -293,12 +294,13 @@
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
-; SI: v_cmp_lt_f32_e32
; SI: v_cmp_lt_f32_e64
+; SI: v_cmp_lt_f32_e32
+
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
-; GCN: v_cndmask_b32_e32
-; GCN: v_cndmask_b32_e64
+; GCN: v_cndmask_b32
+; GCN: v_cndmask_b32
; SI: v_cvt_f16_f32_e32
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm