Added function to set a register to a particular value + tests.
llvm-svn: 342465
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 3b8b1d6..ec488d8 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -34,13 +34,13 @@
const llvm::LLVMTargetMachine &TM, bool &IsComplete) {
IsComplete = true;
std::vector<llvm::MCInst> Result;
- for (const unsigned Reg : RegsToDef) {
- // Load a constant in the register.
- const auto Code = ET.setRegToConstant(*TM.getMCSubtargetInfo(), Reg);
- if (Code.empty())
- IsComplete = false;
- Result.insert(Result.end(), Code.begin(), Code.end());
- }
+ // for (const unsigned Reg : RegsToDef) {
+ // // Load a constant in the register.
+ // const auto Code = ET.setRegToConstant(*TM.getMCSubtargetInfo(), Reg);
+ // if (Code.empty())
+ // IsComplete = false;
+ // Result.insert(Result.end(), Code.begin(), Code.end());
+ // }
return Result;
}