[X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don't have DQI.
We end up using an i8 load via an isel pattern from v8i1 anyway. This just makes it more explicit. This seems to improve codgen in some cases and I'd like to kill off some of the load patterns.
llvm-svn: 321598
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
index a105c0b..8af95df 100644
--- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
+++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
@@ -43,9 +43,7 @@
;
; AVX512-LABEL: bitcast_i2_2i1:
; AVX512: # %bb.0:
-; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; AVX512-NEXT: kmovd %eax, %k1
+; AVX512-NEXT: kmovd %edi, %k1
; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq
@@ -86,9 +84,7 @@
;
; AVX512-LABEL: bitcast_i4_4i1:
; AVX512: # %bb.0:
-; AVX512-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
-; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; AVX512-NEXT: kmovd %eax, %k1
+; AVX512-NEXT: kmovd %edi, %k1
; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: retq