| commit | 87700a734d9ab7174750cf56c65dc9863952a584 | [log] [tgz] |
|---|---|---|
| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | Sun Dec 28 08:54:45 2014 +0000 |
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | Sun Dec 28 08:54:45 2014 +0000 |
| tree | d19c2335d9cfc2e2b14233c2e9515f7b5724bd7e | |
| parent | f2d3bc047406f811c2942de9cd3d84bc4b6c8f54 [diff] |
Scalarizer for masked load and store intrinsics. Masked vector intrinsics are a part of common LLVM IR, but they are really supported on AVX2 and AVX-512 targets. I added a code that translates masked intrinsic for all other targets. The masked vector intrinsic is converted to a chain of scalar operations inside conditional basic blocks. http://reviews.llvm.org/D6436 llvm-svn: 224897