[ARM] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.
This patch also renames FeatureSpecRestrict to FeatureSB.
Reviewed By: olista01, LukeCheeseman
Differential Revision: https://reviews.llvm.org/D55990
llvm-svn: 350299
diff --git a/llvm/include/llvm/Support/ARMTargetParser.def b/llvm/include/llvm/Support/ARMTargetParser.def
index adf6439..e954ac4 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -158,6 +158,7 @@
ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
+ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb")
#undef ARM_ARCH_EXT_NAME
#ifndef ARM_HW_DIV_NAME
diff --git a/llvm/include/llvm/Support/ARMTargetParser.h b/llvm/include/llvm/Support/ARMTargetParser.h
index e41675a..71acc0d 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.h
+++ b/llvm/include/llvm/Support/ARMTargetParser.h
@@ -45,6 +45,7 @@
AEK_SHA2 = 1 << 15,
AEK_AES = 1 << 16,
AEK_FP16FML = 1 << 17,
+ AEK_SB = 1 << 18,
// Unsupported extensions.
AEK_OS = 0x8000000,
AEK_IWMMXT = 0x10000000,
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index b71a098..781d613 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -365,8 +365,8 @@
// Armv8.5-A extensions
-def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
- "Enable speculation control barrier" >;
+def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
+ "Enable v8.5a Speculation Barrier" >;
//===----------------------------------------------------------------------===//
// ARM architecture class
@@ -459,7 +459,7 @@
def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
"Support ARM v8.5a instructions",
- [HasV8_4aOps, FeatureSpecCtrl]>;
+ [HasV8_4aOps, FeatureSB]>;
//===----------------------------------------------------------------------===//
// ARM Processor subtarget features.
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 00f1536..4f42601 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -395,8 +395,8 @@
def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
// Armv8.5-A extensions
-def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
- AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
+def HasSB : Predicate<"Subtarget->hasSB()">,
+ AssemblerPredicate<"FeatureSB", "sb">;
//===----------------------------------------------------------------------===//
// ARM Flag Definitions.
@@ -4895,7 +4895,7 @@
// Armv8.5-A speculation barrier
def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
- Requires<[IsARM, HasSpecCtrl]>, Sched<[]> {
+ Requires<[IsARM, HasSB]>, Sched<[]> {
let Inst{31-0} = 0xf57ff070;
let Unpredictable = 0x000fff0f;
let hasSideEffects = 1;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 4130dbd..18a7ee4 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -3239,7 +3239,7 @@
// Armv8.5-A speculation barrier
def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
- Requires<[IsThumb2, HasSpecCtrl]>, Sched<[]> {
+ Requires<[IsThumb2, HasSB]>, Sched<[]> {
let Inst{31-0} = 0xf3bf8f70;
let Unpredictable = 0x000f2f0f;
let hasSideEffects = 1;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index b06c35f..11841b4 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -417,7 +417,7 @@
bool UseSjLjEH = false;
/// Has speculation barrier
- bool HasSpecCtrl = false;
+ bool HasSB = false;
/// Implicitly convert an instruction to a different one if its immediates
/// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
@@ -628,7 +628,7 @@
bool hasDSP() const { return HasDSP; }
bool useNaClTrap() const { return UseNaClTrap; }
bool useSjLjEH() const { return UseSjLjEH; }
- bool hasSpecCtrl() const { return HasSpecCtrl; }
+ bool hasSB() const { return HasSB; }
bool genLongCalls() const { return GenLongCalls; }
bool genExecuteOnly() const { return GenExecuteOnly; }
diff --git a/llvm/test/MC/ARM/armv8.5a-sb-error-thumb.s b/llvm/test/MC/ARM/armv8.5a-sb-error-thumb.s
new file mode 100644
index 0000000..5f88bf6
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-sb-error-thumb.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
+
+it eq
+sbeq
+
+// CHECK: instruction 'sb' is not predicable, but condition code specified
diff --git a/llvm/test/MC/ARM/armv8.5a-sb-error.s b/llvm/test/MC/ARM/armv8.5a-sb-error.s
new file mode 100644
index 0000000..917b742
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-sb-error.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s 2>&1 | FileCheck %s
+
+sbeq
+
+// CHECK: instruction 'sb' is not predicable
diff --git a/llvm/test/MC/ARM/armv8.5a-sb.s b/llvm/test/MC/ARM/armv8.5a-sb.s
new file mode 100644
index 0000000..f0c9ee4
--- /dev/null
+++ b/llvm/test/MC/ARM/armv8.5a-sb.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s | FileCheck %s
+// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s | FileCheck %s --check-prefix=THUMB
+// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
+// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+// Flag manipulation
+sb
+
+// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
+// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
+
+// NOSB: instruction requires: sb
+// NOSB-NEXT: sb
diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s b/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s
deleted file mode 100644
index 359aec9..0000000
--- a/llvm/test/MC/ARM/armv8.5a-specctrl-error-thumb.s
+++ /dev/null
@@ -1,6 +0,0 @@
-// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
-
-it eq
-sbeq
-
-// CHECK: instruction 'sb' is not predicable, but condition code specified
diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl-error.s b/llvm/test/MC/ARM/armv8.5a-specctrl-error.s
deleted file mode 100644
index 5a018df..0000000
--- a/llvm/test/MC/ARM/armv8.5a-specctrl-error.s
+++ /dev/null
@@ -1,5 +0,0 @@
-// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
-
-sbeq
-
-// CHECK: instruction 'sb' is not predicable
diff --git a/llvm/test/MC/ARM/armv8.5a-specctrl.s b/llvm/test/MC/ARM/armv8.5a-specctrl.s
deleted file mode 100644
index 2d799e6..0000000
--- a/llvm/test/MC/ARM/armv8.5a-specctrl.s
+++ /dev/null
@@ -1,15 +0,0 @@
-// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s
-// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
-// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s --check-prefix=THUMB
-// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
-// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-// Flag manipulation
-sb
-
-// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
-// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
-
-// NOSB: instruction requires: specctrl
-// NOSB-NEXT: sb
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.5a-sb-thumb.txt b/llvm/test/MC/Disassembler/ARM/armv8.5a-sb-thumb.txt
new file mode 100644
index 0000000..f2389f1
--- /dev/null
+++ b/llvm/test/MC/Disassembler/ARM/armv8.5a-sb-thumb.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=thumbv8 -mattr=+sb -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+0xbf 0xf3 0x70 0x8f
+
+# CHECK: sb
+# NOSB: invalid instruction encoding
+# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
diff --git a/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt b/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
deleted file mode 100644
index 5703408..0000000
--- a/llvm/test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-0xbf 0xf3 0x70 0x8f
-
-# CHECK: sb
-# NOSB: invalid instruction encoding
-# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 7fc51ae..3676dee 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -584,7 +584,8 @@
{"iwmmxt", "noiwmmxt", nullptr, nullptr},
{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
{"maverick", "maverick", nullptr, nullptr},
- {"xscale", "noxscale", nullptr, nullptr}};
+ {"xscale", "noxscale", nullptr, nullptr},
+ {"sb", "nosb", "+sb", "-sb"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));