commit 87975df580ccf7ffc73d86dafd52daa662b2c71d
author Evan Cheng <evan.cheng@apple.com> Wed Dec 14 02:28:53 2011 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Dec 14 02:28:53 2011 +0000
tree ed4187ae39379796aa1777c0fbe2717eb82ae712
parent 2be88f13010bd0e730784317ba0175603e110df6

Allow target to specify register output dependency. Still default to one.

llvm-svn: 146547

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index aedc2a1..47c5339 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -278,7 +278,13 @@
         if (DefSU != SU &&
             (Kind != SDep::Output || !MO.isDead() ||
              !DefSU->getInstr()->registerDefIsDead(Reg))) {
-          DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
+          if (Kind == SDep::Anti)
+            DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
+          else {
+            unsigned AOLat = TII->getOutputLatency(InstrItins, MI,
+                                                   DefSU->getInstr(), Reg);
+            DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
+          }
         }
       }
       for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {