Consolidate existing utilities for interpreting vector predicate maskes [NFC]
llvm-svn: 359163
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index fbdc1b7..c60e9d1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -24,7 +24,6 @@
#include "llvm/Analysis/Loads.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Analysis/MemoryBuiltins.h"
-#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/IR/Attributes.h"
@@ -58,6 +57,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/InstCombine/InstCombineWorklist.h"
+#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/SimplifyLibCalls.h"
#include <algorithm>
#include <cassert>
@@ -1147,36 +1147,6 @@
return Builder.CreateShuffleVector(V1, V2, ShuffleMask);
}
-static bool maskIsAllOneOrUndef(Value *Mask) {
- auto *ConstMask = dyn_cast<Constant>(Mask);
- if (!ConstMask)
- return false;
- if (ConstMask->isAllOnesValue() || isa<UndefValue>(ConstMask))
- return true;
- for (unsigned I = 0, E = ConstMask->getType()->getVectorNumElements(); I != E;
- ++I) {
- if (auto *MaskElt = ConstMask->getAggregateElement(I))
- if (MaskElt->isAllOnesValue() || isa<UndefValue>(MaskElt))
- continue;
- return false;
- }
- return true;
-}
-
-/// Given a mask vector <Y x i1>, return an APInt (of bitwidth Y) for each lane
-/// which may be active. TODO: This is a lot like known bits, but for
-/// vectors. Is there something we can common this with?
-static APInt possiblyDemandedEltsInMask(Value *Mask) {
-
- const unsigned VWidth = cast<VectorType>(Mask->getType())->getNumElements();
- APInt DemandedElts = APInt::getAllOnesValue(VWidth);
- if (auto *CV = dyn_cast<ConstantVector>(Mask))
- for (unsigned i = 0; i < VWidth; i++)
- if (CV->getAggregateElement(i)->isNullValue())
- DemandedElts.clearBit(i);
- return DemandedElts;
-}
-
// TODO, Obvious Missing Transforms:
// * Narrow width by halfs excluding zero/undef lanes
Value *InstCombiner::simplifyMaskedLoad(IntrinsicInst &II) {