commit 88faf6d6979dff876aabbec690b7096d123f3092
author Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> Mon Nov 16 17:05:01 2015 +0000
committer Vasileios Kalintiris <Vasileios.Kalintiris@imgtec.com> Mon Nov 16 17:05:01 2015 +0000
tree e7de1ce1e4bbef175feedfc1884ab0dbb87d2526
parent ed5cc95d2297f9a7c12ea6a4fd3c517c5bc9dfac

[mips] Disable code generation through FastISel for MIPS32R6.

Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14708

llvm-svn: 253225

llvm/lib/Target/Mips/MipsFastISel.cpp

diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 23b0215..e9eaf81 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -192,10 +192,10 @@
         TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
     Context = &funcInfo.Fn->getContext();
+    bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
     TargetSupported =
-        ((TM.getRelocationModel() == Reloc::PIC_) &&
-         ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
-          (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
+        ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
+        (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
     UnsupportedFPMode = Subtarget->isFP64bit();
   }