commit 8931fde869c2787886a5f84c03f70cd32e2e8b1f
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jan 14 13:01:46 2020 -0500
committer Matt Arsenault <arsenm2@gmail.com> Wed Jan 15 08:58:57 2020 -0500
tree 8c3f507e91543a79a827b25341b282fab7ab1f68
parent eafa8dbefe30c85e58efc5309793f2d7c2109e35

TableGen: Delete some copy constuctors

Some register related machinery relies on uniqued, static pointers for
register classes and subregisters, so try to make sure these are never
copied.

llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 96e4f95..01cb659 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -141,7 +141,7 @@
   assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
   assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
                                                     " a RegisterClass\n");
-  CodeGenRegisterClass RC = Target.getRegisterClass(RegClass);
+  const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
   const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
   assert((R != nullptr) &&
          ("Register" + Reg->getName().str() + " not defined!!\n").c_str());
@@ -160,8 +160,8 @@
 
   if (DagOpType->isSubClassOf("RegisterClass") &&
       InstOpType->isSubClassOf("RegisterClass")) {
-    CodeGenRegisterClass RC = Target.getRegisterClass(InstOpType);
-    CodeGenRegisterClass SubRC = Target.getRegisterClass(DagOpType);
+    const CodeGenRegisterClass &RC = Target.getRegisterClass(InstOpType);
+    const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType);
     return RC.hasSubClass(&SubRC);
   }