commit 8adb9944aafd95a15264f27fc02eeecbde1d1d94
author Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:02:22 2003 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:02:22 2003 +0000
tree 34462566d8a9913c788234ee1d688579046149fd
parent 196897c42457211b000ca17e9e90f5cee75ba2a5

Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

llvm/lib/Target/Sparc/EmitAssembly.cpp

diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp
index 1509fdbb..f6761d0 100644
--- a/llvm/lib/Target/Sparc/EmitAssembly.cpp
+++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp
@@ -302,7 +302,7 @@
   void emitMachineInst(const MachineInstr *MI);
   
   unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
-  void printOneOperand(const MachineOperand &Op);
+  void printOneOperand(const MachineOperand &Op, MachineOpCode opCode);
 
   bool OpIsBranchTargetLabel(const MachineInstr *MI, unsigned int opNum);
   bool OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum);
@@ -341,10 +341,10 @@
 }
 
 
-#define PrintOp1PlusOp2(mop1, mop2) \
-  printOneOperand(mop1); \
+#define PrintOp1PlusOp2(mop1, mop2, opCode) \
+  printOneOperand(mop1, opCode); \
   toAsm << "+"; \
-  printOneOperand(mop2);
+  printOneOperand(mop2, opCode);
 
 unsigned int
 SparcFunctionAsmPrinter::printOperands(const MachineInstr *MI,
@@ -354,26 +354,26 @@
   
   if (OpIsBranchTargetLabel(MI, opNum))
     {
-      PrintOp1PlusOp2(mop, MI->getOperand(opNum+1));
+      PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
       return 2;
     }
   else if (OpIsMemoryAddressBase(MI, opNum))
     {
       toAsm << "[";
-      PrintOp1PlusOp2(mop, MI->getOperand(opNum+1));
+      PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
       toAsm << "]";
       return 2;
     }
   else
     {
-      printOneOperand(mop);
+      printOneOperand(mop, MI->getOpCode());
       return 1;
     }
 }
 
-
 void
-SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop)
+SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop,
+                                         MachineOpCode opCode)
 {
   bool needBitsFlag = true;
   
@@ -394,13 +394,13 @@
     case MachineOperand::MO_CCRegister:
     case MachineOperand::MO_MachineRegister:
       {
-        int RegNum = (int)mop.getAllocatedRegNum();
+        int regNum = (int)mop.getAllocatedRegNum();
         
-        // better to print code with NULL registers than to die
-        if (RegNum == Target.getRegInfo().getInvalidRegNum()) {
+        if (regNum == Target.getRegInfo().getInvalidRegNum()) {
+          // better to print code with NULL registers than to die
           toAsm << "<NULL VALUE>";
         } else {
-          toAsm << "%" << Target.getRegInfo().getUnifiedRegName(RegNum);
+          toAsm << "%" << Target.getRegInfo().getUnifiedRegName(regNum);
         }
         break;
       }