commit 8adb9944aafd95a15264f27fc02eeecbde1d1d94
author Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:02:22 2003 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Tue May 27 00:02:22 2003 +0000
tree 34462566d8a9913c788234ee1d688579046149fd
parent 196897c42457211b000ca17e9e90f5cee75ba2a5

Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

llvm/lib/Target/Sparc/SparcRegClassInfo.h

diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
index a8a39eb..bc9b445 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
@@ -63,7 +63,7 @@
      StartOfAllRegs = o0,
   };
 
-  static const char * const getRegName(unsigned reg);
+  const char * const getRegName(unsigned reg) const;
 };
 
 
@@ -104,7 +104,7 @@
     StartOfAllRegs = f0,
   };
 
-  static const char * const getRegName(unsigned reg);
+  const char * const getRegName(unsigned reg) const;
 };
 
 
@@ -138,7 +138,7 @@
     xcc, ccr   // only one is available - see the note above
   };
 
-  static const char * const getRegName(unsigned reg);
+  const char * const getRegName(unsigned reg) const;
 };
 
 
@@ -146,12 +146,12 @@
 
 //-----------------------------------------------------------------------------
 // Float CC Register Class
-// Only 4 Float CC registers are available
+// Only 4 Float CC registers are available for allocation.
 //-----------------------------------------------------------------------------
 
 struct SparcFloatCCRegClass : public TargetRegClassInfo {
   SparcFloatCCRegClass(unsigned ID) 
-    : TargetRegClassInfo(ID, 4, 4) {  }
+    : TargetRegClassInfo(ID, 4, 5) {  }
 
   void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
     for(unsigned c = 0; c != 4; ++c)
@@ -168,10 +168,33 @@
   inline bool isRegVolatile(int Reg) const { return true; }
 
   enum {
-    fcc0, fcc1, fcc2, fcc3
+    fcc0, fcc1, fcc2, fcc3, fsr         // fsr is not used in allocation
+  };                                    // but has a name in getRegName()
+
+  const char * const getRegName(unsigned reg) const;
+};
+
+//-----------------------------------------------------------------------------
+// Sparc special register class.  These registers are not used for allocation
+// but are used as arguments of some instructions.
+//-----------------------------------------------------------------------------
+
+struct SparcSpecialRegClass : public TargetRegClassInfo {
+  SparcSpecialRegClass(unsigned ID) 
+    : TargetRegClassInfo(ID, 0, 1) {  }
+
+  void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
+    assert(0 && "SparcSpecialRegClass should never be used for allocation");
+  }
+  
+  // all currently included special regs are volatile
+  inline bool isRegVolatile(int Reg) const { return true; }
+
+  enum {
+    fsr                                 // floating point state register
   };
 
-  static const char * const getRegName(unsigned reg);
+  const char * const getRegName(unsigned reg) const;
 };
 
 #endif