commit 8af61ddb960dfe4a71d7b130fa3ca87c94ecc1cf
author Chris Lattner <sabre@nondot.org> Mon Aug 16 01:10:21 2004 +0000
committer Chris Lattner <sabre@nondot.org> Mon Aug 16 01:10:21 2004 +0000
tree 86f943713028fdff95c50aa5fded64848f4cfd72
parent b7b70480e1a480f364e1327ac5b6507f055a66f7

Use CodeGenRegister class to make reading in of register information more
systematic.

llvm-svn: 15805

llvm/utils/TableGen/CodeGenTarget.h

diff --git a/llvm/utils/TableGen/CodeGenTarget.h b/llvm/utils/TableGen/CodeGenTarget.h
index 218fef8..2d65b7b 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/CodeGenTarget.h
@@ -17,6 +17,7 @@
 #ifndef CODEGEN_TARGET_H
 #define CODEGEN_TARGET_H
 
+#include "CodeGenRegisters.h"
 #include "CodeGenInstruction.h"
 #include <iosfwd>
 #include <map>
@@ -25,6 +26,7 @@
 
 class Record;
 class RecordKeeper;
+class CodeGenRegister;
 
 /// getValueType - Return the MVT::ValueType that the specified TableGen record
 /// corresponds to.
@@ -43,7 +45,9 @@
   MVT::ValueType PointerType;
 
   mutable std::map<std::string, CodeGenInstruction> Instructions;
+  mutable std::vector<CodeGenRegister> Registers;
   void ReadInstructions() const;
+  void ReadRegisters() const;
 public:
   CodeGenTarget();
 
@@ -64,8 +68,10 @@
   ///
   Record *getAsmWriter() const;
 
-  /// getPHIInstruction - Return the designated PHI instruction.
-  const CodeGenInstruction &getPHIInstruction() const;
+  const std::vector<CodeGenRegister> &getRegisters() {
+    if (Registers.empty()) ReadRegisters();
+    return Registers;
+  }
 
   /// getInstructions - Return all of the instructions defined for this target.
   ///
@@ -78,6 +84,10 @@
                    CodeGenInstruction>::const_iterator inst_iterator;
   inst_iterator inst_begin() const { return getInstructions().begin(); }
   inst_iterator inst_end() const { return Instructions.end(); }
+
+  /// getPHIInstruction - Return the designated PHI instruction.
+  ///
+  const CodeGenInstruction &getPHIInstruction() const;
 };
 
 } // End llvm namespace