commit 8b20fa42dace77c5bddae44a167002b47bdf26d2
author Andrew Lenharth <andrewl@lenharth.org> Tue Oct 31 19:52:12 2006 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Tue Oct 31 19:52:12 2006 +0000
tree d9d64f33c7ba358d6266f3c77dc0644c95d0d87d
parent c24140f8a7810104e5a944049cb224eb97bc57c9

Let us play simplify the td file (and fix a few missed sub and mul patterns).

llvm-svn: 31322

llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 15ee143..0903abb 100644
--- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -122,6 +122,14 @@
         return comphigh;
     }
 
+    static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
+      uint64_t y = getNearPower2(x);
+      if (swap)
+        return (y - x) == r;
+      else
+        return (x - y) == r;
+    }
+
     static bool isFPZ(SDOperand N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
       return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));