Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
diff --git a/llvm/test/CodeGen/ARM/phi.ll b/llvm/test/CodeGen/ARM/phi.ll
index 29e17c0..dc1a95b 100644
--- a/llvm/test/CodeGen/ARM/phi.ll
+++ b/llvm/test/CodeGen/ARM/phi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm < %s | FileCheck %s
+; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s
; <rdar://problem/8686347>
define i32 @test1(i1 %a, i32* %b) {
@@ -20,4 +20,4 @@
%r = load i32* %gep
; CHECK-NEXT: bx lr
ret i32 %r
-}
\ No newline at end of file
+}