commit 8b2f70125fb8e6e1ee72e6f5175ba20703afd248
author Kalle Raiskila <kalle.raiskila@nokia.com> Wed Aug 04 13:59:48 2010 +0000
committer Kalle Raiskila <kalle.raiskila@nokia.com> Wed Aug 04 13:59:48 2010 +0000
tree 93935c2a7f37d29e22527a89e3cb990044b70d4b
parent 61c8e6dc16b15f1466959a0c5eea991dfe83b224

Make SPU backend handle insertelement and 
store for "half vectors"

llvm-svn: 110198

llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 9b8c2dd..e42417c 100644
--- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -607,7 +607,8 @@
     return true;
   } else if (Opc == ISD::Register 
            ||Opc == ISD::CopyFromReg 
-           ||Opc == ISD::UNDEF) {
+           ||Opc == ISD::UNDEF
+           ||Opc == ISD::Constant) {
     unsigned OpOpc = Op->getOpcode();
 
     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {

llvm/lib/Target/CellSPU/SPUISelLowering.cpp

diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 3a945ce..7a6bb0f 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2102,7 +2102,10 @@
   SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
                                 DAG.getRegister(SPU::R1, PtrVT),
                                 DAG.getConstant(Idx, PtrVT));
-  SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
+  // widen the mask when dealing with half vectors
+  EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(), 
+                                128/ VT.getVectorElementType().getSizeInBits());
+  SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, maskVT, Pointer);
 
   SDValue result =
     DAG.getNode(SPUISD::SHUFB, dl, VT,

llvm/lib/Target/CellSPU/SPUInstrInfo.td

diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td
index 803ce56..f1d0886 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td
@@ -63,6 +63,7 @@
     def v2f64: LoadDFormVec<v2f64>;
 
     def v2i32: LoadDFormVec<v2i32>;
+    def v2f32: LoadDFormVec<v2f32>;
 
     def r128:  LoadDForm<GPRC>;
     def r64:   LoadDForm<R64C>;
@@ -97,6 +98,7 @@
     def v2f64: LoadAFormVec<v2f64>;
 
     def v2i32: LoadAFormVec<v2i32>;
+    def v2f32: LoadAFormVec<v2f32>;
 
     def r128:  LoadAForm<GPRC>;
     def r64:   LoadAForm<R64C>;
@@ -131,6 +133,7 @@
     def v2f64: LoadXFormVec<v2f64>;
 
     def v2i32: LoadXFormVec<v2i32>;
+    def v2f32: LoadXFormVec<v2f32>;
 
     def r128:  LoadXForm<GPRC>;
     def r64:   LoadXForm<R64C>;
@@ -181,6 +184,7 @@
   def v2f64: StoreDFormVec<v2f64>;
 
   def v2i32: StoreDFormVec<v2i32>;
+  def v2f32: StoreDFormVec<v2f32>;
 
   def r128:  StoreDForm<GPRC>;
   def r64:   StoreDForm<R64C>;
@@ -213,6 +217,7 @@
   def v2f64: StoreAFormVec<v2f64>;
 
   def v2i32: StoreAFormVec<v2i32>;
+  def v2f32: StoreAFormVec<v2f32>;
 
   def r128:  StoreAForm<GPRC>;
   def r64:   StoreAForm<R64C>;
@@ -247,6 +252,7 @@
   def v2f64: StoreXFormVec<v2f64>;
 
   def v2i32: StoreXFormVec<v2i32>;
+  def v2f32: StoreXFormVec<v2f32>;
 
   def r128:  StoreXForm<GPRC>;
   def r64:   StoreXForm<R64C>;